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qemu/include/hw/riscv
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Alistair Francis fe0fe4735e riscv: Initial commit of OpenTitan machine 
This adds a barebone OpenTitan machine to QEMU.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-06-03 09:11:51 -07:00
..
boot.h
riscv/boot: Add a missing header include
2020-06-03 09:11:51 -07:00
opentitan.h
riscv: Initial commit of OpenTitan machine
2020-06-03 09:11:51 -07:00
riscv_hart.h
riscv: hart: Add a "hartid-base" property to RISC-V hart array
2019-09-17 08:42:47 -07:00
riscv_htif.h
Clean up inclusion of sysemu/sysemu.h
2019-08-16 13:31:53 +02:00
sifive_clint.h
hw/riscv: Provide rdtime callback for TCG in CLINT emulation
2020-02-27 13:46:37 -08:00
sifive_cpu.h
riscv: Add a sifive_cpu.h to include both E and U cpu type defines
2019-09-17 08:42:46 -07:00
sifive_e_prci.h
riscv: sifive_e: prci: Update the PRCI register block size
2019-09-17 08:42:46 -07:00
sifive_e.h
riscv: sifive_e: Manually define the machine
2020-06-03 09:11:51 -07:00
sifive_gpio.h
SiFive RISC-V GPIO Device
2019-05-24 11:58:30 -07:00
sifive_plic.h
riscv: plic: Remove unused interrupt functions
2019-09-17 08:42:42 -07:00
sifive_test.h
riscv: sifive_test: Add reset functionality
2019-09-17 08:42:44 -07:00
sifive_u_otp.h
riscv: sifive: Implement a model for SiFive FU540 OTP
2019-09-17 08:42:49 -07:00
sifive_u_prci.h
riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes
2019-09-17 08:42:48 -07:00
sifive_u.h
riscv/sifive_u: Add a serial property to the sifive_u machine
2020-04-29 13:16:36 -07:00
sifive_uart.h
include: Make headers more self-contained
2019-08-16 13:31:51 +02:00
spike.h
hw/riscv: spike: Remove deprecated ISA specific machines
2020-06-03 09:11:51 -07:00
virt.h
riscv: virt: Use Goldfish RTC device
2020-02-10 12:01:38 -08:00