Rob Bradford 2571a6427c target/riscv: Use existing PMU counter mask in FDT generation ...

During the FDT generation use the existing mask containing the enabled
counters rather then generating a new one. Using the existing mask will
support the use of discontinuous counters.

Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Message-ID: <20231031154000.18134-4-rbradford@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

2023-11-07 11:06:02 +10:00

..

boot.c

target/riscv: rename ext_icsr to ext_zicsr

2023-11-07 11:02:17 +10:00

Kconfig

hw/riscv: sifive_e: Support the watchdog timer of HiFive 1 rev b.

2023-07-10 22:29:15 +10:00

meson.build

hw/riscv/virt: Enable basic ACPI infrastructure

2023-03-06 11:35:04 -08:00

microchip_pfsoc.c

riscv: spelling fixes

2023-09-08 13:08:52 +03:00

numa.c

hw/riscv: Fix typo field in error_report

2023-07-19 14:31:41 +10:00

opentitan.c

hw/riscv: opentitan: Fixup local variables shadowing

2023-09-29 10:07:20 +02:00

riscv_hart.c

hw/riscv: hart: Add a new 'resetvec' property

2020-09-09 15:54:18 -07:00

shakti_c.c

*: Add missing includes of qemu/error-report.h

2023-03-22 15:06:57 +00:00

sifive_e.c

hw/riscv: sifive_e: Support the watchdog timer of HiFive 1 rev b.

2023-07-10 22:29:15 +10:00

sifive_u.c

hw/sd: Introduce a "sd-card" SPI variant model

2023-09-01 11:40:04 +02:00

spike.c

hw/riscv: Validate cluster and NUMA node boundary

2023-06-26 10:23:01 +02:00

virt-acpi-build.c

*: Add missing includes of qemu/error-report.h

2023-03-22 15:06:57 +00:00

virt.c

target/riscv: Use existing PMU counter mask in FDT generation

2023-11-07 11:06:02 +10:00