Stafford Horne 13f1c77364 openrisc: Initial SMP support ...

Wire in ompic and add basic support for SMP.  The OpenRISC is special in
that interrupts for devices are routed to each core's PIC.  This is
achieved using the qemu_irq_split utility, but this currently limits
OpenRISC to 2 cores.

This models the reference architecture described in the OpenRISC spec
1.2 proposal.

  https://github.com/stffrdhrn/doc/raw/arch-1.2-proposal/openrisc-arch-1.2-rev0.pdf

The changes to the intialization of the sim include:

CPU Reset
 o Reset each cpu to the bootstrap PC rather than only a single cpu as
   done before.
 o During Kernel loading the bootstrap PC is saved in a static global.

Network Initialization
 o Connect the interrupt to each CPU
 o Use more simple sysbus_mmio_map() rather than memory_region_add_subregion()

Sim Initialization
 o Initialize the pic and tick timer per cpu
 o Wire in the OMPIC if SMP is enabled
 o Wire the serial irq to each CPU using qemu_irq_split()

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>

2017-10-21 06:36:58 +09:00

..

cputimer.c

openrisc/cputimer: Perparation for Multicore

2017-10-21 06:35:47 +09:00

Makefile.objs

hw: move boards and other isolated files to hw/ARCH

2013-03-01 15:01:19 +01:00

openrisc_sim.c

openrisc: Initial SMP support

2017-10-21 06:36:58 +09:00

pic_cpu.c

openrisc: Clean up includes

2016-01-29 15:07:24 +00:00