Richard Henderson 001dddfe0e tcg/riscv: Introduce prepare_host_addr ...

Merge tcg_out_tlb_load, add_qemu_ldst_label, tcg_out_test_alignment,
and some code that lived in both tcg_out_qemu_ld and tcg_out_qemu_st
into one function that returns TCGReg and TCGLabelQemuLdst.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

2023-05-11 09:53:41 +01:00

..

tcg-target-con-set.h

tcg/riscv: Require TCG_TARGET_REG_BITS == 64

2023-05-05 17:21:03 +01:00

tcg-target-con-str.h

tcg/riscv: Split out target constraints to tcg-target-con-str.h

2021-02-02 12:12:31 -10:00

tcg-target.c.inc

tcg/riscv: Introduce prepare_host_addr

2023-05-11 09:53:41 +01:00

tcg-target.h

tcg/riscv: Require TCG_TARGET_REG_BITS == 64

2023-05-05 17:21:03 +01:00