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stable-5.0
qemu/include/hw/riscv
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Anup Patel 5f3616ccce hw/riscv: Provide rdtime callback for TCG in CLINT emulation 
This patch extends CLINT emulation to provide rdtime callback for
TCG. This rdtime callback will be called wheneven TIME CSRs are
read in privileged modes.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2020-02-27 13:46:37 -08:00
..
boot.h
hw/riscv: Add optional symbol callback ptr to riscv_load_kernel()
2019-11-25 12:34:52 -08:00
riscv_hart.h
riscv: hart: Add a "hartid-base" property to RISC-V hart array
2019-09-17 08:42:47 -07:00
riscv_htif.h
Clean up inclusion of sysemu/sysemu.h
2019-08-16 13:31:53 +02:00
sifive_clint.h
hw/riscv: Provide rdtime callback for TCG in CLINT emulation
2020-02-27 13:46:37 -08:00
sifive_cpu.h
riscv: Add a sifive_cpu.h to include both E and U cpu type defines
2019-09-17 08:42:46 -07:00
sifive_e_prci.h
riscv: sifive_e: prci: Update the PRCI register block size
2019-09-17 08:42:46 -07:00
sifive_e.h
riscv: Add a sifive_cpu.h to include both E and U cpu type defines
2019-09-17 08:42:46 -07:00
sifive_gpio.h
SiFive RISC-V GPIO Device
2019-05-24 11:58:30 -07:00
sifive_plic.h
riscv: plic: Remove unused interrupt functions
2019-09-17 08:42:42 -07:00
sifive_test.h
riscv: sifive_test: Add reset functionality
2019-09-17 08:42:44 -07:00
sifive_u_otp.h
riscv: sifive: Implement a model for SiFive FU540 OTP
2019-09-17 08:42:49 -07:00
sifive_u_prci.h
riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes
2019-09-17 08:42:48 -07:00
sifive_u.h
riscv/sifive_u: Add the start-in-flash property
2019-10-28 07:47:28 -07:00
sifive_uart.h
include: Make headers more self-contained
2019-08-16 13:31:51 +02:00
spike.h
riscv: hw: Drop "clock-frequency" property of cpu nodes
2019-10-28 07:47:27 -07:00
virt.h
riscv: virt: Use Goldfish RTC device
2020-02-10 12:01:38 -08:00