Michael Clark 4a67f4a953 RISC-V: Minimal QEMU 2.12 fix for sifive_u machine ...

The 'sifive_u' board has a bug where the ROM is
created as RAM at the wrong address and marked
readonly. The bug renders the board unusable.
This is a minimal fix and allows booting Linux.

5aec3247c1
"RISC-V: Mark ROM read-only after copying in code"
contains a comprehensive fix using the ROM APIs
memory_region_init_rom and rom_add_blob_fixed_as
which could be backported.

Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Cc: qemu-stable@nongnu.org
Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>

2018-07-18 10:32:06 -05:00

..

Makefile.objs

RISC-V Build Infrastructure

2018-03-07 08:30:28 +13:00

riscv_hart.c

…

riscv_htif.c

riscv: htif: increase the priority of the htif subregion

2018-07-11 11:48:22 -05:00

sifive_clint.c

SiFive RISC-V CLINT Block

2018-03-07 08:30:28 +13:00

sifive_e.c

SiFive Freedom E Series RISC-V Machine

2018-03-07 08:30:28 +13:00

sifive_plic.c

SiFive RISC-V PLIC Block

2018-03-07 08:30:28 +13:00

sifive_prci.c

SiFive RISC-V PRCI Block

2018-03-07 08:30:28 +13:00

sifive_test.c

SiFive RISC-V Test Finisher

2018-03-07 08:30:28 +13:00

sifive_u.c

RISC-V: Minimal QEMU 2.12 fix for sifive_u machine

2018-07-18 10:32:06 -05:00

sifive_uart.c

SiFive RISC-V UART Device

2018-03-07 08:30:28 +13:00

spike.c

RISC-V Spike Machines

2018-03-07 08:30:28 +13:00

virt.c

RISC-V VirtIO Machine

2018-03-07 08:30:28 +13:00