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qemu/include/hw/riscv
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Manos Pitsidianakis b1470a14b3 hw/riscv/virt.h: correct typos 
Correct typos automatically found with the `typos` tool
<https://crates.io/crates/typos>

Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Michael Tokarev <mjt@tls.msk.ru>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2024-02-21 08:16:43 +03:00
..
boot_opensbi.h
include: Include headers where needed
2023-01-08 01:54:22 -05:00
boot.h
hw/riscv/boot.c: make riscv_load_initrd() static
2023-02-16 07:55:37 -08:00
microchip_pfsoc.h
include: Include headers where needed
2023-01-08 01:54:22 -05:00
numa.h
hw/riscv: use ms->fdt in riscv_socket_fdt_write_distance_matrix()
2023-01-20 10:14:14 +10:00
opentitan.h
hw/riscv/opentitan: Correct OpenTitanState parent type/size
2023-06-13 17:19:42 +10:00
riscv_hart.h
riscv: spelling fixes
2023-09-08 13:08:52 +03:00
shakti_c.h
hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0
2023-01-06 10:42:55 +10:00
sifive_cpu.h
riscv: Add a sifive_cpu.h to include both E and U cpu type defines
2019-09-17 08:42:46 -07:00
sifive_e.h
hw/riscv: sifive_e: Support the watchdog timer of HiFive 1 rev b.
2023-07-10 22:29:15 +10:00
sifive_u.h
hw/riscv: Move the dtb load bits outside of create_fdt()
2023-03-01 17:19:14 -08:00
spike.h
hw/riscv/spike: use 'fdt' from MachineState
2023-01-20 10:14:13 +10:00
virt.h
hw/riscv/virt.h: correct typos
2024-02-21 08:16:43 +03:00