92b30c2f7d
hw/intc/arm_gicv3: Add missing break
...
These are spotted by coverity 1356936 and 1356937.
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org >
Message-id: 1466387717-13740-1-git-send-email-zhaoshenglong@huawei.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2016-06-27 15:37:32 +01:00
227a865366
hw/intc/arm_gicv3: Add IRQ handling CPU interface registers
...
Add the CPU interface registers which deal with acknowledging
and dismissing interrupts.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org >
Tested-by: Shannon Zhao <shannon.zhao@linaro.org >
Message-id: 1465915112-29272-19-git-send-email-peter.maydell@linaro.org
2016-06-17 15:23:51 +01:00
b1a0eb777d
hw/intc/arm_gicv3: Implement CPU i/f SGI generation registers
...
Implement the registers in the GICv3 CPU interface which generate
new SGI interrupts.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org >
Tested-by: Shannon Zhao <shannon.zhao@linaro.org >
Message-id: 1465915112-29272-18-git-send-email-peter.maydell@linaro.org
2016-06-17 15:23:51 +01:00
f7b9358e2c
hw/intc/arm_gicv3: Implement gicv3_cpuif_update()
...
Implement the gicv3_cpuif_update() function which deals with correctly
asserting IRQ and FIQ based on the current running priority of the CPU,
the priority of the highest priority pending interrupt and the CPU's
current exception level and security state.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org >
Tested-by: Shannon Zhao <shannon.zhao@linaro.org >
Message-id: 1465915112-29272-17-git-send-email-peter.maydell@linaro.org
2016-06-17 15:23:51 +01:00
359fbe65e0
hw/intc/arm_gicv3: Implement GICv3 CPU interface registers
...
Implement the CPU interface registers for the GICv3; these are
CPU system registers, not MMIO registers.
This commit implements all the registers which are simple
accessors for GIC state, but not those which act as interfaces
for acknowledging, dismissing or generating interrupts. (Those
will be added in a later commit.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org >
Tested-by: Shannon Zhao <shannon.zhao@linaro.org >
Message-id: 1465915112-29272-16-git-send-email-peter.maydell@linaro.org
2016-06-17 15:23:51 +01:00
