f7697f0e62
target/riscv: Add basic vmstate description of CPU
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Add basic CPU state description to the newly created machine.c
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com >
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20201026115530.304-3-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2020-11-03 07:17:23 -08:00
00e925c560
target/riscv: Check nanboxed inputs to fp helpers
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If a 32-bit input is not properly nanboxed, then the input is
replaced with the default qnan.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com >
Message-Id: <20200724002807.441147-5-richard.henderson@linaro.org >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2020-08-21 22:37:55 -07:00
9921e3d330
target/riscv: Generate nanboxed results from fp helpers
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Make sure that all results from single-precision scalar helpers
are properly nan-boxed to 64-bits.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com >
Message-Id: <20200724002807.441147-2-richard.henderson@linaro.org >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2020-08-21 22:37:55 -07:00
9fc08be626
target/riscv: integer scalar move instruction
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Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20200701152549.1218-57-zhiwei_liu@c-sky.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2020-07-02 09:19:33 -07:00
121ddbb36f
target/riscv: vector floating-point classify instructions
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Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20200701152549.1218-41-zhiwei_liu@c-sky.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2020-07-02 09:19:33 -07:00
268fcca66b
target/riscv: add vector amo operations
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Vector AMOs operate as if aq and rl bits were zero on each element
with regard to ordering relative to other instructions in the same hart.
Vector AMOs provide no ordering guarantee between element operations
in the same vector AMO instruction
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20200701152549.1218-10-zhiwei_liu@c-sky.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2020-07-02 09:19:33 -07:00
751538d5da
target/riscv: add vector stride load and store instructions
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Vector strided operations access the first memory element at the base address,
and then access subsequent elements at address increments given by the byte
offset contained in the x register specified by rs2.
Vector unit-stride operations access elements stored contiguously in memory
starting from the base effective address. It can been seen as a special
case of strided operations.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20200701152549.1218-7-zhiwei_liu@c-sky.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2020-07-02 09:19:32 -07:00
f476f17740
target/riscv: add an internals.h header
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The internals.h keeps things that are not relevant to the actual architecture,
only to the implementation, separate.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20200701152549.1218-6-zhiwei_liu@c-sky.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2020-07-02 09:19:32 -07:00
