71ed30b7d4
target/mips: Allow Loongson 3A1000 to use up to 48-bit VAddr
...
Per the manual '龙芯 GS264 处理器核用户手册' v1.0, chapter
1.1.5 SEGBITS: the 3A1000 (based on GS464 core) implements
48 virtual address bits in each 64-bit segment, not 40.
Fixes: af868995e1f4bug@amsat.org >
Reviewed-by: Huacai Chen <chenhuacai@loongson.cn >
Message-Id: <20210813110149.1432692-3-f4bug@amsat.org >
2021-08-25 13:02:14 +02:00
98d207cf9c
target/mips: Document Loongson-3A CPU definitions
...
Document the cores on which each Loongson-3A CPU is based (see
commit af868995e1f4bug@amsat.org >
Reviewed-by: Huacai Chen <chenhuacai@loongson.cn >
Message-Id: <20210813110149.1432692-2-f4bug@amsat.org >
2021-08-25 13:02:14 +02:00
eaca85763b
target/mips: Remove vendor specific CPU definitions
...
Vendor specific CPU definitions are not very useful. Use the
ISA definitions instead, which are more helpful when looking
at the various CPU definitions.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20210112210152.2072996-4-f4bug@amsat.org >
2021-01-14 17:13:54 +01:00
fc63010e9b
target/mips: Remove CPU_NANOMIPS32 definition
...
nanoMIPS not a CPU, but an ISA. The nanoMIPS ISA is already
defined as ISA_NANOMIPS32.
Remove this incorrect definition and update the single CPU
implementing it, the I7200.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20210112210152.2072996-3-f4bug@amsat.org >
2021-01-14 17:13:54 +01:00
03e4d95c91
target/mips: Move msa_reset() to msa_helper.c
...
translate_init.c.inc mostly contains CPU definitions.
msa_reset() doesn't belong here, move it with the MSA
helpers.
One comment style is updated to avoid checkpatch.pl warning.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20201215225757.764263-15-f4bug@amsat.org >
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com >
2021-01-14 17:13:53 +01:00
7e2a619a04
target/mips: Remove now unused ASE_MSA definition
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We don't use ASE_MSA anymore (replaced by ase_msa_available()
checking MSAP bit from CP0_Config3). Remove it.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com >
Message-Id: <20201208003702.4088927-6-f4bug@amsat.org >
2021-01-14 17:13:53 +01:00
72f31f60f8
target/mips: Simplify msa_reset()
...
Call msa_reset() unconditionally, but only reset
the MSA registers if MSA is implemented.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com >
Message-Id: <20201208003702.4088927-3-f4bug@amsat.org >
2021-01-14 17:13:53 +01:00
0dc351ca6b
target/mips: Rename translate_init.c as cpu-defs.c
...
This file is not TCG specific, contains CPU definitions
and is consumed by cpu.c. Rename it as such.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20201214183739.500368-10-f4bug@amsat.org >
2021-01-14 17:13:53 +01:00
