92371bd903
target/riscv: Add MXL/SXL/UXL to TB_FLAGS
...
Begin adding support for switching XLEN at runtime. Extract the
effective XLEN from MISA and MSTATUS and store for use during translation.
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20211020031709.359469-6-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-10-22 07:47:51 +10:00
db23e5d981
target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl
...
Shortly, the set of supported XL will not be just 32 and 64,
and representing that properly using the enumeration will be
imperative.
Two places, booting and gdb, intentionally use misa_mxl_max
to emphasize the use of the reset value of misa.mxl, and not
the current cpu state.
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20211020031709.359469-5-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-10-22 07:47:51 +10:00
e91a7227cb
target/riscv: Split misa.mxl and misa.ext
...
The hw representation of misa.mxl is at the high bits of the
misa csr. Representing this in the same way inside QEMU
results in overly complex code trying to check that field.
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20211020031709.359469-4-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-10-22 07:47:51 +10:00
9d3d60b704
target/riscv: Organise the CPU properties
...
Organise the CPU properties so that standard extensions come first
then followed by experimental extensions.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Message-id: b6598570f60c5ee7f402be56d837bb44b289cc4d.1634531504.git.alistair.francis@wdc.com
2021-10-22 07:47:51 +10:00
e573a7f325
target/riscv: line up all of the registers in the info register dump
...
Ensure the columns for all of the register names and values line up.
No functional change, just a minor tweak to the output.
Signed-off-by: Travis Geiselbrecht <travisg@gmail.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20211009055019.545153-1-travisg@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-10-22 07:47:51 +10:00
9916ea3c97
target/riscv: Remove RVB (replaced by Zb[abcs])
...
With everything classified as Zb[abcs] and pre-0.93 draft-B
instructions that are not part of Zb[abcs] removed, we can remove the
remaining support code for RVB.
Note that RVB has been retired for good and misa.B will neither mean
'some' or 'all of' Zb*:
https://lists.riscv.org/g/tech-bitmanip/message/532
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Message-id: 20210911140016.834071-16-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-10-07 08:41:33 +10:00
878dd0e9ac
target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties
...
The bitmanipulation ISA extensions will be ratified as individual
small extension packages instead of a large B-extension. The first
new instructions through the door (these have completed public review)
are Zb[abcs].
This adds new 'x-zba', 'x-zbb', 'x-zbc' and 'x-zbs' properties for
these in target/riscv/cpu.[ch].
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Message-id: 20210911140016.834071-5-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-10-07 08:32:55 +10:00
0f0b70eeec
target/riscv: Expose interrupt pending bits as GPIO lines
...
Expose the 12 interrupt pending bits in MIP as GPIO lines.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Tested-by: Bin Meng <bmeng.cn@gmail.com >
Message-id: 069d6162f0bc2f4a4f5a44e73f6442b11c703c53.1630301632.git.alistair.francis@wdc.com
2021-09-21 07:56:49 +10:00
a44da25aa6
target/riscv: Update the ePMP CSR address
...
Update the ePMP CSRs to match the 0.9.3 ePMP spec
6145574723/Smepmp/Smepmp.pdfalistair.francis@wdc.com >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Message-id: 28c908de60b9b04fa20e63d113885c98586053f3.1630543194.git.alistair.francis@wdc.com
2021-09-21 07:56:49 +10:00
17b3c353e6
target/riscv: Restrict cpu_exec_interrupt() handler to sysemu
...
Restrict cpu_exec_interrupt() and its callees to sysemu.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Reviewed-by: Warner Losh <imp@bsdimp.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Message-Id: <20210911165434.531552-19-f4bug@amsat.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2021-09-14 12:00:21 -07:00
a8b37120d4
target/riscv: Don't wrongly override isa version
...
For some cpu, the isa version has already been set in cpu init function.
Thus only override the isa version when isa version is not set, or
users set different isa version explicitly by cpu parameters.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Message-id: 20210811144612.68674-1-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-09-01 11:59:12 +10:00
d2c1a177b1
target/riscv: rvb: add b-ext version cpu option
...
Default b-ext version is v0.93.
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20210505160620.15723-18-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-06-08 09:59:46 +10:00
d52e94081e
target/riscv: rvb: support and turn on B-extension from command line
...
B-extension is default off, use cpu rv32 or rv64 with x-b=true to
enable B-extension.
Signed-off-by: Kito Cheng <kito.cheng@sifive.com >
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20210505160620.15723-17-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-06-08 09:59:46 +10:00
a722701dd3
target/riscv: Dump CSR mscratch/sscratch/satp
...
This dumps the CSR mscratch/sscratch/satp and meanwhile aligns
the output of CSR mtval/stval.
Signed-off-by: Changbin Du <changbin.du@gmail.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Message-id: 20210519155738.20486-1-changbin.du@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-06-08 09:59:43 +10:00
9a575d33fb
target/riscv: Remove unnecessary riscv_*_names[] declaration
...
riscv_excp_names[] and riscv_intr_names[] are only referenced by
target/riscv/cpu.c locally.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com >
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20210514052435.2203156-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-06-08 09:59:43 +10:00
119065574d
hw/core: Constify TCGCPUOps
...
We no longer have any runtime modifications to this struct,
so declare them all const.
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-ID: <20210227232519.222663-3-richard.henderson@linaro.org >
2021-05-26 15:33:59 -07:00
08928c6d0d
cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOps
...
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20210517105140.1062037-21-f4bug@amsat.org >
[rth: Drop declaration movement from target/*/cpu.h]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2021-05-26 15:33:59 -07:00
715e3c1afb
cpu: Move CPUClass::write_elf* to SysemuCPUOps
...
The write_elf*() handlers are used to dump vmcore images.
This feature is only meaningful for system emulation.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20210517105140.1062037-19-f4bug@amsat.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2021-05-26 15:33:59 -07:00
feece4d070
cpu: Move CPUClass::vmsd to SysemuCPUOps
...
Migration is specific to system emulation.
- Move the CPUClass::vmsd field to SysemuCPUOps,
- restrict VMSTATE_CPU() macro to sysemu,
- vmstate_dummy is now unused, remove it.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20210517105140.1062037-16-f4bug@amsat.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2021-05-26 15:33:59 -07:00
8b80bd28a5
cpu: Introduce SysemuCPUOps structure
...
Introduce a structure to hold handler specific to sysemu.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20210517105140.1062037-15-f4bug@amsat.org >
[rth: Squash "restrict hw/core/sysemu-cpu-ops.h" patch]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2021-05-26 15:33:59 -07:00
744c72a837
cpu: Rename CPUClass vmsd -> legacy_vmsd
...
Quoting Peter Maydell [*]:
There are two ways to handle migration for
a CPU object:
(1) like any other device, so it has a dc->vmsd that covers
migration for the whole object. As usual for objects that are a
subclass of a parent that has state, the first entry in the
VMStateDescription field list is VMSTATE_CPU(), which migrates
the cpu_common fields, followed by whatever the CPU's own migration
fields are.
(2) a backwards-compatible mechanism for CPUs that were
originally migrated using manual "write fields to the migration
stream structures". The on-the-wire migration format
for those is based on the 'env' pointer (which isn't a QOM object),
and the cpu_common part of the migration data is elsewhere.
cpu_exec_realizefn() handles both possibilities:
* for type 1, dc->vmsd is set and cc->vmsd is not,
so cpu_exec_realizefn() does nothing, and the standard
"register dc->vmsd for a device" code does everything needed
* for type 2, dc->vmsd is NULL and so we register the
vmstate_cpu_common directly to handle the cpu-common fields,
and the cc->vmsd to handle the per-CPU stuff
You can't change a CPU from one type to the other without breaking
migration compatibility, which is why some guest architectures
are stuck on the cc->vmsd form. New targets should use dc->vmsd.
To avoid new targets to start using type (2), rename cc->vmsd as
cc->legacy_vmsd. The correct field to implement is dc->vmsd (the
DeviceClass one).
See also commit b170fce3ddhttps://www.mail-archive.com/qemu-devel@nongnu.org/msg800849.html
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Cc: Peter Maydell <peter.maydell@linaro.org >
Message-Id: <20210517105140.1062037-13-f4bug@amsat.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2021-05-26 15:33:59 -07:00
3820602f80
target/riscv: Remove the hardcoded RVXLEN macro
...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Message-id: a07bc0c6dc4958681b4f93cbc5d0acc31ed3344a.1619234854.git.alistair.francis@wdc.com
2021-05-11 20:02:07 +10:00
6cfcf77573
target/riscv: fix a typo with interrupt names
...
Interrupt names have been swapped in 205377f8emmanuel.blot@sifive.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20210421133236.11323-1-emmanuel.blot@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-05-11 20:02:07 +10:00
ed6eebaaaf
target/riscv: Add ePMP support for the Ibex CPU
...
The physical Ibex CPU has ePMP support and it's enabled for the
OpenTitan machine so let's enable ePMP support for the Ibex CPU in QEMU.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Message-id: d426baabab0c9361ed2e989dbe416e417a551fd1.1618812899.git.alistair.francis@wdc.com
2021-05-11 20:02:06 +10:00
5da9514e96
target/riscv: Add a config option for ePMP
...
Add a config option to enable experimental support for ePMP. This
is disabled by default and can be enabled with 'x-epmp=true'.
Signed-off-by: Hongzheng-Li <Ethan.Lee.QNL@gmail.com >
Signed-off-by: Hou Weiying <weiying_hou@outlook.com >
Signed-off-by: Myriad-Dreamin <camiyoru@gmail.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Message-id: a22ccdaf9314078bc735d3b323f966623f8af020.1618812899.git.alistair.francis@wdc.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
2021-05-11 20:02:06 +10:00
330d2ae32a
target/riscv: Convert the RISC-V exceptions to an enum
...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: f191dcf08bf413a822e743a7c7f824d68879a527.1617290165.git.alistair.francis@wdc.com
2021-05-11 20:02:06 +10:00
6ddc7069f5
target/riscv: Add Shakti C class CPU
...
C-Class is a member of the SHAKTI family of processors from IIT-M.
It is an extremely configurable and commercial-grade 5-stage in-order
core supporting the standard RV64GCSUN ISA extensions.
Signed-off-by: Vijai Kumar K <vijai@behindbytes.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20210401181457.73039-2-vijai@behindbytes.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-05-11 20:01:10 +10:00
01e723bf18
target/riscv: Align the data type of reset vector address
...
Use target_ulong to instead of uint64_t on reset vector address
to adapt on both 32/64 machine.
Signed-off-by: Dylan Jhong <dylan@andestech.com >
Signed-off-by: Ruinland ChuanTzu Tsai <ruinland@andestech.com >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20210329034801.22667-1-dylan@andestech.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-05-11 20:01:10 +10:00
ac12b60103
target/riscv: Remove privilege v1.9 specific CSR related code
...
Qemu doesn't support RISC-V privilege specification v1.9. Remove the
remaining v1.9 specific references from the implementation.
Signed-off-by: Atish Patra <atish.patra@wdc.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20210319194534.2082397-2-atish.patra@wdc.com >
[Changes by AF:
- Rebase on latest patches
- Bump the vmstate_riscv_cpu version_id and minimum_version_id
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-05-11 20:01:10 +10:00
ec352d0cab
target/riscv: Add proper two-stage lookup exception detection
...
The current two-stage lookup detection in riscv_cpu_do_interrupt falls
short of its purpose, as all it checks is whether two-stage address
translation either via the hypervisor-load store instructions or the
MPRV feature would be allowed.
What we really need instead is whether two-stage address translation was
active when the exception was raised. However, in riscv_cpu_do_interrupt
we do not have the information to reliably detect this. Therefore, when
we raise a memory fault exception we have to record whether two-stage
address translation is active.
Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20210319141459.1196741-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-03-22 21:54:40 -04:00
cba42d61a3
Various spelling fixes
...
An assorted set of spelling fixes in various places.
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru >
Reviewed-by: Stefan Weil <sw@weilnetz.de >
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com >
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Message-Id: <20210309111510.79495-1-mjt@msgid.tls.msk.ru >
Signed-off-by: Laurent Vivier <laurent@vivier.eu >
2021-03-09 21:19:10 +01:00
43a9658889
target-riscv: support QMP dump-guest-memory
...
Add the support needed for creating prstatus elf notes. This allows
us to use QMP dump-guest-memory.
Now ELF notes of RISC-V only contain prstatus elf notes.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com >
Signed-off-by: Mingwang Li <limingwang@huawei.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Andrew Jones <drjones@redhat.com >
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com >
Message-id: 20210201124458.1248-2-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-03-04 09:43:29 -05:00
7827168471
cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass
...
we cannot in principle make the TCG Operations field definitions
conditional on CONFIG_TCG in code that is included by both common_ss
and specific_ss modules.
Therefore, what we can do safely to restrict the TCG fields to TCG-only
builds, is to move all tcg cpu operations into a separate header file,
which is only included by TCG, target-specific code.
This leaves just a NULL pointer in the cpu.h for the non-TCG builds.
This also tidies up the code in all targets a bit, having all TCG cpu
operations neatly contained by a dedicated data struct.
Signed-off-by: Claudio Fontana <cfontana@suse.de >
Message-Id: <20210204163931.7358-16-cfontana@suse.de >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2021-02-05 10:24:15 -10:00
8535dd702d
cpu: move do_unaligned_access to tcg_ops
...
make it consistently SOFTMMU-only.
Signed-off-by: Claudio Fontana <cfontana@suse.de >
Reviewed-by: Alex Bennée <alex.bennee@linaro.org >
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
[claudio: make the field presence in cpu.h unconditional, removing the ifdefs]
Message-Id: <20210204163931.7358-12-cfontana@suse.de >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2021-02-05 10:24:14 -10:00
cbc183d2d9
cpu: move cc->transaction_failed to tcg_ops
...
Signed-off-by: Claudio Fontana <cfontana@suse.de >
Reviewed-by: Alex Bennée <alex.bennee@linaro.org >
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
[claudio: wrap target code around CONFIG_TCG and !CONFIG_USER_ONLY]
avoiding its use in headers used by common_ss code (should be poisoned).
Note: need to be careful with the use of CONFIG_USER_ONLY,
Message-Id: <20210204163931.7358-11-cfontana@suse.de >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2021-02-05 10:24:14 -10:00
0545608056
cpu: move cc->do_interrupt to tcg_ops
...
Signed-off-by: Claudio Fontana <cfontana@suse.de >
Reviewed-by: Alex Bennée <alex.bennee@linaro.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20210204163931.7358-10-cfontana@suse.de >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2021-02-05 10:24:14 -10:00
e124536f37
cpu: Move tlb_fill to tcg_ops
...
[claudio: wrapped target code in CONFIG_TCG]
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com >
Signed-off-by: Claudio Fontana <cfontana@suse.de >
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com >
Reviewed-by: Alex Bennée <alex.bennee@linaro.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20210204163931.7358-7-cfontana@suse.de >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2021-02-05 10:24:14 -10:00
48c1a3e303
cpu: Move cpu_exec_* to tcg_ops
...
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com >
[claudio: wrapped target code in CONFIG_TCG]
Signed-off-by: Claudio Fontana <cfontana@suse.de >
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com >
Reviewed-by: Alex Bennée <alex.bennee@linaro.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20210204163931.7358-6-cfontana@suse.de >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2021-02-05 10:24:14 -10:00
ec62595bab
cpu: Move synchronize_from_tb() to tcg_ops
...
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com >
[claudio: wrapped target code in CONFIG_TCG, reworded comments]
Signed-off-by: Claudio Fontana <cfontana@suse.de >
Reviewed-by: Alex Bennée <alex.bennee@linaro.org >
Message-Id: <20210204163931.7358-5-cfontana@suse.de >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2021-02-05 10:24:14 -10:00
6a3d2e7c06
target/riscv: remove CONFIG_TCG, as it is always TCG
...
for now only TCG is allowed as an accelerator for riscv,
so remove the CONFIG_TCG use.
Signed-off-by: Claudio Fontana <cfontana@suse.de >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Alex Bennée <alex.bennee@linaro.org >
Message-Id: <20210204163931.7358-3-cfontana@suse.de >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2021-02-05 10:24:14 -10:00
e9e51b7154
cpu: Introduce TCGCpuOperations struct
...
The TCG-specific CPU methods will be moved to a separate struct,
to make it easier to move accel-specific code outside generic CPU
code in the future. Start by moving tcg_initialize().
The new CPUClass.tcg_opts field may eventually become a pointer,
but keep it an embedded struct for now, to make code conversion
easier.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com >
[claudio: move TCGCpuOperations inside include/hw/core/cpu.h]
Reviewed-by: Alex Bennée <alex.bennee@linaro.org >
Message-Id: <20210204163931.7358-2-cfontana@suse.de >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2021-02-05 10:24:14 -10:00
b93777e1b4
target/riscv: Generate the GDB XML file for CSR registers dynamically
...
At present QEMU RISC-V uses a hardcoded XML to report the feature
"org.gnu.gdb.riscv.csr" [1]. There are two major issues with the
approach being used currently:
- The XML does not specify the "regnum" field of a CSR entry, hence
consecutive numbers are used by the remote GDB client to access
CSRs. In QEMU we have to maintain a map table to convert the GDB
number to the hardware number which is error prone.
- The XML contains some CSRs that QEMU does not implement at all,
which causes an "E14" response sent to remote GDB client.
Change to generate the CSR register list dynamically, based on the
availability presented in the CSR function table. This new approach
will reflect a correct list of CSRs that QEMU actually implements.
[1] https://sourceware.org/gdb/current/onlinedocs/gdb/RISC_002dV-Features.html#RISC_002dV-Features
Signed-off-by: Bin Meng <bin.meng@windriver.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20210116054123.5457-2-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-01-16 10:57:21 -08:00
edf647864b
gdb: riscv: Add target description
...
Target description is not currently implemented in RISC-V
architecture. Thus GDB won't set it properly when attached.
The patch implements the target description response.
Signed-off-by: Sylvain Pelissier <sylvain.pelissier@gmail.com >
Reviewed-by: Bin Meng <bin.meng@windriver.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Message-id: 20210106204141.14027-1-sylvain.pelissier@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-01-16 10:57:21 -08:00
04a37d4ca4
tcg: Make tb arg to synchronize_from_tb const
...
There is nothing within the translators that ought to be
changing the TranslationBlock data, so make it const.
This does not actually use the read-only copy of the
data structure that exists within the rx region.
Reviewed-by: Joelle van Dyne <j@getutm.app >
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2021-01-07 05:09:41 -10:00
094b072c68
target/riscv: cpu: Set XLEN independently from target
...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Bin Meng <bin.meng@windriver.com >
Tested-by: Bin Meng <bin.meng@windriver.com >
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com >
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com >
Message-id: 7eddba45b5d223321c031431849fdd42eceb514b.1608142916.git.alistair.francis@wdc.com
2020-12-17 21:56:44 -08:00
5c5a47f10c
target/riscv: cpu: Remove compile time XLEN checks
...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Bin Meng <bin.meng@windriver.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com >
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com >
Tested-by: Bin Meng <bin.meng@windriver.com >
Message-id: a426ead44db5065a0790066d43e91245683509d7.1608142916.git.alistair.francis@wdc.com
2020-12-17 21:56:44 -08:00
114baaca51
target/riscv: Specify the XLEN for CPUs
...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Bin Meng <bin.meng@windriver.com >
Tested-by: Bin Meng <bin.meng@windriver.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com >
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com >
Message-id: c1da66affbb83ec4a2fbeb0194293bd24d65f5dc.1608142916.git.alistair.francis@wdc.com
2020-12-17 21:56:44 -08:00
51ae0cabc6
target/riscv: Add a riscv_cpu_is_32bit() helper function
...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Bin Meng <bin.meng@windriver.com >
Tested-by: Bin Meng <bin.meng@windriver.com >
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com >
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com >
Message-id: ebd37b237a8cbe457335b948bd57f487b6b31869.1608142916.git.alistair.francis@wdc.com
2020-12-17 21:56:44 -08:00
f7697f0e62
target/riscv: Add basic vmstate description of CPU
...
Add basic CPU state description to the newly created machine.c
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com >
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20201026115530.304-3-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2020-11-03 07:17:23 -08:00
284d697c74
target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit
...
mstatus/mstatush and vsstatus/vsstatush are two halved for RISCV32.
This patch expands mstatus and vsstatus to uint64_t instead of
target_ulong so that it can be saved as one unit and reduce some
ifdefs in the code.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com >
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20201026115530.304-2-jiangyifei@huawei.com
2020-11-03 07:17:23 -08:00
