268fcca66b
target/riscv: add vector amo operations
...
Vector AMOs operate as if aq and rl bits were zero on each element
with regard to ordering relative to other instructions in the same hart.
Vector AMOs provide no ordering guarantee between element operations
in the same vector AMO instruction
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20200701152549.1218-10-zhiwei_liu@c-sky.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2020-07-02 09:19:33 -07:00
022b4ecf77
target/riscv: add fault-only-first unit stride load
...
The unit-stride fault-only-fault load instructions are used to
vectorize loops with data-dependent exit conditions(while loops).
These instructions execute as a regular load except that they
will only take a trap on element 0.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20200701152549.1218-9-zhiwei_liu@c-sky.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2020-07-02 09:19:33 -07:00
f732560e35
target/riscv: add vector index load and store instructions
...
Vector indexed operations add the contents of each element of the
vector offset operand specified by vs2 to the base effective address
to give the effective address of each element.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20200701152549.1218-8-zhiwei_liu@c-sky.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2020-07-02 09:19:33 -07:00
751538d5da
target/riscv: add vector stride load and store instructions
...
Vector strided operations access the first memory element at the base address,
and then access subsequent elements at address increments given by the byte
offset contained in the x register specified by rs2.
Vector unit-stride operations access elements stored contiguously in memory
starting from the base effective address. It can been seen as a special
case of strided operations.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20200701152549.1218-7-zhiwei_liu@c-sky.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2020-07-02 09:19:32 -07:00
2b7168fc43
target/riscv: add vector configure instruction
...
vsetvl and vsetvli are two configure instructions for vl, vtype. TB flags
should update after configure instructions. The (ill, lmul, sew ) of vtype
and the bit of (VSTART == 0 && VL == VLMAX) will be placed within tb_flags.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20200701152549.1218-5-zhiwei_liu@c-sky.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2020-07-02 09:19:32 -07:00
