3a16ecb063
target-tricore: Add instructions of BO opcode format
...
Add instructions of BO opcode format.
Add microcode generator functions gen_swap, gen_ldmst.
Add microcode generator functions gen_st/ld_preincr, which write back the address after the memory access.
Add helper for circular and bit reverse addr mode calculation.
Add sign extended bitmask for BO_OFF10 field.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de >
Reviewed-by: Richard Henderson <rth@twiddle.net >
2014-10-20 12:25:07 +01:00
59543d4ee1
target-tricore: Add instructions of ABS, ABSB opcode format
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Add instructions of ABS, ABSB opcode format.
Add microcode generator functions for ld/st of two 32bit reg as one 64bit value.
Add microcode generator functions for ldmst and swap.
Add helper ldlcx, lducx, stlcx and stucx.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de >
Reviewed-by: Richard Henderson <rth@twiddle.net >
2014-10-20 12:25:07 +01:00
44ea34309e
target-tricore: Add instructions of SR opcode format
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Add instructions of SR opcode format.
Add micro-op generator functions for saturate.
Add helper return from exception (rfe).
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de >
Message-id: 1409572800-4116-16-git-send-email-kbastian@mail.uni-paderborn.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2014-09-01 14:49:21 +01:00
5de93515f9
target-tricore: Add instructions of SC opcode format
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Add instructions of SC opcode format.
Add helper for begin interrupt service routine.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de >
Message-id: 1409572800-4116-14-git-send-email-kbastian@mail.uni-paderborn.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2014-09-01 14:49:21 +01:00
9a31922b08
target-tricore: Add instructions of SB opcode format
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Add instructions of SB opcode format.
Add helper call/ret.
Add micro-op generator functions for branches.
Add makro to generate helper functions.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de >
Message-id: 1409572800-4116-11-git-send-email-kbastian@mail.uni-paderborn.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2014-09-01 14:49:21 +01:00
2692802a37
target-tricore: Add instructions of SRR opcode format
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Add instructions of SRR opcode format.
Add helper for add/sub_ssov.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de >
Message-id: 1409572800-4116-8-git-send-email-kbastian@mail.uni-paderborn.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2014-09-01 14:49:21 +01:00
0707ec1bea
target-tricore: Add instructions of SRC opcode format
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Add instructions of SRC opcode format.
Add micro-op generator functions for add, conditional add/sub and shi/shai.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de >
Reviewed-by: Richard Henderson <rth@twiddle.net >
Message-id: 1409572800-4116-7-git-send-email-kbastian@mail.uni-paderborn.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2014-09-01 14:49:20 +01:00
48e06fe0ed
target-tricore: Add target stubs and qom-cpu
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Add TriCore target stubs, and QOM cpu, and Maintainer
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de >
Message-id: 1409572800-4116-2-git-send-email-kbastian@mail.uni-paderborn.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2014-09-01 14:49:20 +01:00
