8700ee15de
hw/cxl: Standardize all references on CXL r3.1 and minor updates
...
Previously not all references mentioned any spec version at all.
Given r3.1 is the current specification available for evaluation at
www.computeexpresslink.org update references to refer to that.
Hopefully this won't become a never ending job.
A few structure definitions have been updated to add new fields.
Defaults of 0 and read only are valid choices for these new DVSEC
registers so go with that for now.
There are additional error codes and some of the 'questions' in
the comments are resolved now.
Update documentation reference to point to the CXL r3.1 specification
with naming closer to what is on the cover.
For cases where there are structure version numbers, add defines
so they can be found next to the register definitions.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com >
Message-Id: <20240126121636.24611-6-Jonathan.Cameron@huawei.com >
Reviewed-by: Michael S. Tsirkin <mst@redhat.com >
Signed-off-by: Michael S. Tsirkin <mst@redhat.com >
2024-02-14 06:09:33 -05:00
314f5033c6
hw/pci-bridge/cxl_downstream: Set default link width and link speed
...
Without these being set the PCIE Link Capabilities register has
invalid values in these two fields.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com >
Message-Id: <20231023160806.13206-10-Jonathan.Cameron@huawei.com >
Reviewed-by: Michael S. Tsirkin <mst@redhat.com >
Signed-off-by: Michael S. Tsirkin <mst@redhat.com >
2023-11-07 03:39:11 -05:00
3314efd276
hw/cxl/mbox: Add Physical Switch Identify command.
...
Enable it for the switch CCI.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com >
Message-Id: <20231023160806.13206-9-Jonathan.Cameron@huawei.com >
Reviewed-by: Michael S. Tsirkin <mst@redhat.com >
Signed-off-by: Michael S. Tsirkin <mst@redhat.com >
2023-11-07 03:39:11 -05:00
b34ae3c906
hw/cxl: CXLDVSECPortExtensions renamed to CXLDVSECPortExt
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Done to reduce line lengths where this is used.
Ext seems sufficiently obvious that it need not be spelt out
fully.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com >
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org >
Reviewed-by: Fan Ni <fan.ni@samsung.com >
Message-Id: <20231023140210.3089-4-Jonathan.Cameron@huawei.com >
Reviewed-by: Michael S. Tsirkin <mst@redhat.com >
Signed-off-by: Michael S. Tsirkin <mst@redhat.com >
2023-11-07 03:39:11 -05:00
f1c0cff8a2
hw/pci: spelling fixes
...
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru >
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
2023-09-20 07:54:34 +03:00
9518d8bc44
hw/pci-bridge/cxl_downstream: Fix type naming mismatch
...
Fix capitalization difference between struct name and typedef.
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org >
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org >
Reviewed-by: Ira Weiny <ira.weiny@intel.com >
Reviewed-by: Gregory Price <gregory.price@memverge.com >
Tested-by: Gregory Price <gregory.price@memverge.com >
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com >
Message-Id: <20230206172816.8201-3-Jonathan.Cameron@huawei.com >
Reviewed-by: Fan Ni <fan.ni@samsung.com >
Reviewed-by: Michael S. Tsirkin <mst@redhat.com >
Signed-off-by: Michael S. Tsirkin <mst@redhat.com >
2023-03-02 19:13:52 -05:00
ad4942746c
pci: drop redundant PCIDeviceClass::is_bridge field
...
and use cast to TYPE_PCI_BRIDGE instead.
Signed-off-by: Igor Mammedov <imammedo@redhat.com >
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org >
Message-Id: <20221129101341.185621-3-imammedo@redhat.com >
Reviewed-by: Michael S. Tsirkin <mst@redhat.com >
Signed-off-by: Michael S. Tsirkin <mst@redhat.com >
Reviewed-by: Greg Kurz <groug@kaod.org >
2022-12-21 07:32:24 -05:00
18cef1c6a5
pci-bridge/cxl_downstream: Add a CXL switch downstream port
...
Emulation of a simple CXL Switch downstream port.
The Device ID has been allocated for this use.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com >
Message-Id: <20220616145126.8002-3-Jonathan.Cameron@huawei.com >
Signed-off-by: Michael S. Tsirkin <mst@redhat.com >
Reviewed-by: Michael S. Tsirkin <mst@redhat.com >
Signed-off-by: Michael S. Tsirkin <mst@redhat.com >
2022-06-16 12:54:57 -04:00
