2b434dd127
tcg: Search includes in the parent source directory
...
All the *.inc.c files included by tcg/$TARGET/tcg-target.inc.c
are in tcg/, their parent directory. To simplify the preprocessor
search path, include the relative parent path: '..'.
Patch created mechanically by running:
$ for x in tcg-pool.inc.c tcg-ldst.inc.c; do \
sed -i "s,#include \"$x\",#include \"../$x\"," \
$(git grep -l "#include \"$x\""); \
done
Acked-by: David Gibson <david@gibson.dropbear.id.au > (ppc parts)
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Stefan Weil <sw@weilnetz.de >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com >
Message-Id: <20200101112303.20724-3-philmd@redhat.com >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2020-01-15 15:13:10 -10:00
14776ab5a1
tcg: TCGMemOp is now accelerator independent MemOp
...
Preparation for collapsing the two byte swaps, adjust_endianness and
handle_bswap, along the I/O path.
Target dependant attributes are conditionalized upon NEED_CPU_H.
Signed-off-by: Tony Nguyen <tony.nguyen@bt.com >
Acked-by: David Gibson <david@gibson.dropbear.id.au >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Acked-by: Cornelia Huck <cohuck@redhat.com >
Message-Id: <81d9cd7d7f5aaadfa772d6c48ecee834e9cf7882.1566466906.git.tony.nguyen@bt.com >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2019-09-03 08:30:38 -07:00
7ab7e9c7c7
tcg/riscv: Fix RISC-VH host build failure
...
Commit 269bd5d8
"cpu: Move the softmmu tlb to CPUNegativeOffsetState'
broke the RISC-V host build as there are two variables that are used but
not defined.
This patch renames the undefined variables mask_off and table_off to the
existing (but unused) mask_ofs and table_ofs variables.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <79729cc88ca509e08b5c4aa0aa8a52847af70c0f.1561039316.git.alistair.francis@wdc.com >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2019-07-09 08:26:11 +02:00
269bd5d8f6
cpu: Move the softmmu tlb to CPUNegativeOffsetState
...
We have for some time had code within the tcg backends to
handle large positive offsets from env. This move makes
sure that need not happen. Indeed, we are able to assert
at build time that simple offsets suffice for all hosts.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2019-06-10 07:03:42 -07:00
a40ec84ee2
tcg: Create struct CPUTLB
...
Move all softmmu tlb data into this structure. Arrange the
members so that we are able to place mask+table together and
at a smaller absolute offset from ENV.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Acked-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2019-06-10 07:03:34 -07:00
78113e83e0
tcg: Return bool success from tcg_out_mov
...
This patch merely changes the interface, aborting on all failures,
of which there are currently none.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org >
Reviewed-by: David Hildenbrand <david@redhat.com >
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com >
Reviewed-by: David Gibson <david@gibson.dropbear.id.au >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2019-05-13 14:44:03 -07:00
aeee05f53a
tcg: Restart TB generation after out-of-line ldst overflow
...
This is part c of relocation overflow handling.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2019-04-24 13:05:28 -07:00
41b70f220b
tcg/riscv: enable dynamic TLB sizing
...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2019-01-28 07:04:24 -08:00
7a5549f2ae
tcg/riscv: Add the target init code
...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Michael Clark <mjc@sifive.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <dd6e439ab81883974b8fd91f904f6de26ab5d697.1545246859.git.alistair.francis@wdc.com >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2018-12-26 06:40:02 +11:00
92c041c59b
tcg/riscv: Add the prologue generation and register the JIT
...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Michael Clark <mjc@sifive.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <c4d023127967a0217d8d1eabdf5de6c0e8f8c228.1545246859.git.alistair.francis@wdc.com >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2018-12-26 06:40:02 +11:00
bdf503819e
tcg/riscv: Add the out op decoder
...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Michael Clark <mjc@sifive.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <7c47f00cb4a9a777120456e0704b4076a5d943ab.1545246859.git.alistair.francis@wdc.com >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2018-12-26 06:40:02 +11:00
03a7d0213d
tcg/riscv: Add direct load and store instructions
...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Michael Clark <mjc@sifive.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <2e047a95c39c007c66cda024c095e29b0ac4c43e.1545246859.git.alistair.francis@wdc.com >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2018-12-26 06:40:02 +11:00
efbea94c76
tcg/riscv: Add slowpath load and store instructions
...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Michael Clark <mjc@sifive.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <1a0a7e8f3347764f212c5efa5c07c9be17efdec6.1545246859.git.alistair.francis@wdc.com >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2018-12-26 06:40:02 +11:00
15840069e1
tcg/riscv: Add branch and jump instructions
...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Michael Clark <mjc@sifive.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <c356657e627168d89cb5b012b7e21e4efbbe83f3.1545246859.git.alistair.francis@wdc.com >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2018-12-26 06:40:02 +11:00
28ca738e9d
tcg/riscv: Add the add2 and sub2 instructions
...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <5665a57809e32b35775e8e98fdab898853af37b8.1545246859.git.alistair.francis@wdc.com >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2018-12-26 06:40:02 +11:00
61535d4988
tcg/riscv: Add the out load and store instructions
...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Michael Clark <mjc@sifive.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <d5d88ff29163788938368bbdbd18815d59cef6a0.1545246859.git.alistair.francis@wdc.com >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2018-12-26 06:40:02 +11:00
27fd64144b
tcg/riscv: Add the extract instructions
...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Michael Clark <mjc@sifive.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <c4d2afba46efefa9388cf3205fcedbb9a5fa411f.1545246859.git.alistair.francis@wdc.com >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2018-12-26 06:40:02 +11:00
6cd2eda39f
tcg/riscv: Add the mov and movi instruction
...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Michael Clark <mjc@sifive.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <bd6a45c73a67b77ddaa2fe590a6bb8ee422b9683.1545246859.git.alistair.francis@wdc.com >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2018-12-26 06:40:02 +11:00
dfa8e74f94
tcg/riscv: Add the relocation functions
...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Michael Clark <mjc@sifive.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <6ac4f4b0d5ea93cb0ee9a3b8b47ee9f7b3711494.1545246859.git.alistair.francis@wdc.com >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2018-12-26 06:40:02 +11:00
bedf14e335
tcg/riscv: Add the instruction emitters
...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Michael Clark <mjc@sifive.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <c740aca183675625bb9cf3ce7b9e8b9d431ca694.1545246859.git.alistair.francis@wdc.com >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2018-12-26 06:40:02 +11:00
54a9ce0f68
tcg/riscv: Add the immediate encoders
...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Michael Clark <mjc@sifive.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <d54dc56303fd1b0d7ed53869de2dbb59b111c7ca.1545246859.git.alistair.francis@wdc.com >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2018-12-26 06:40:02 +11:00
8ce23a1312
tcg/riscv: Add support for the constraints
...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Michael Clark <mjc@sifive.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <dba7315e4e20e879933f72d47ccf98f1cc612b8a.1545246859.git.alistair.francis@wdc.com >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2018-12-26 06:40:02 +11:00
505e75c592
tcg/riscv: Add the tcg target registers
...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Michael Clark <mjc@sifive.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <6e43abaa64361d57b9bc9439820d0e7701f2d47e.1545246859.git.alistair.francis@wdc.com >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2018-12-26 06:40:02 +11:00