bbb9fc2591
target/riscv: Simplify type conversion for CPURISCVState
...
Use CPURISCVState as argument directly in riscv_cpu_update_mip and
riscv_timer_write_timecmp, since type converts from CPURISCVState to
RISCVCPU in many caller of them and then back to CPURISCVState in them.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn >
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com >
Message-Id: <20230309071329.45932-4-liweiwei@iscas.ac.cn >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-05-05 10:49:49 +10:00
ae0edf2188
target/riscv: No need to re-start QEMU timer when timecmp == UINT64_MAX
...
The time CSR will wrap-around immediately after reaching UINT64_MAX
so we don't need to re-start QEMU timer when timecmp == UINT64_MAX
in riscv_timer_write_timecmp().
Signed-off-by: Anup Patel <apatel@ventanamicro.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20230120125950.2246378-4-apatel@ventanamicro.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-02-07 08:19:23 +10:00
14cb78bfaf
target/riscv: Don't clear mask in riscv_cpu_update_mip() for VSTIP
...
Instead of clearing mask in riscv_cpu_update_mip() for VSTIP, we
should call riscv_cpu_update_mip() with mask == 0 from timer_helper.c
for VSTIP.
Fixes: 3ec0fe18a3apatel@ventanamicro.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20230120125950.2246378-3-apatel@ventanamicro.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-02-07 08:19:22 +10:00
3ec0fe18a3
target/riscv: Add vstimecmp support
...
vstimecmp CSR allows the guest OS or to program the next guest timer
interrupt directly. Thus, hypervisor no longer need to inject the
timer interrupt to the guest if vstimecmp is used. This was ratified
as a part of the Sstc extension.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Atish Patra <atishp@rivosinc.com >
Message-Id: <20220824221357.41070-4-atishp@rivosinc.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-09-07 09:19:15 +02:00
43888c2f18
target/riscv: Add stimecmp support
...
stimecmp allows the supervisor mode to update stimecmp CSR directly
to program the next timer interrupt. This CSR is part of the Sstc
extension which was ratified recently.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Atish Patra <atishp@rivosinc.com >
Message-Id: <20220824221357.41070-3-atishp@rivosinc.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-09-07 09:19:15 +02:00
