fafe0021e3
target/*: Add missing includes of tcg/debug-assert.h
...
This had been pulled in from tcg/tcg.h, via exec/cpu_ldst.h,
via exec/exec-all.h, but the include of tcg.h will be removed.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2023-06-05 12:04:28 -07:00
604b66ce5e
target/avr: Replace tb_pc() with tb->pc
...
Signed-off-by: Anton Johansson <anjo@rev.ng >
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org >
Message-Id: <20230227135202.9710-26-anjo@rev.ng >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2023-03-01 07:33:24 -10:00
605787606e
target/avr: Convert to 3-phase reset
...
Convert the avr CPU class to use 3-phase reset, so it doesn't
need to use device_class_set_parent_reset() any more.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Cédric Le Goater <clg@kaod.org >
Message-id: 20221124115023.2437291-4-peter.maydell@linaro.org
2022-12-16 15:58:15 +00:00
f06c1ad4c6
target/avr: Convert to tcg_ops restore_state_to_opc
...
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2022-10-26 11:11:28 +10:00
fbf59aad17
accel/tcg: Introduce tb_pc and log_pc
...
The availability of tb->pc will shortly be conditional.
Introduce accessor functions to minimize ifdefs.
Pass around a known pc to places like tcg_gen_code,
where the caller must already have the value.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2022-10-04 12:13:12 -07:00
e4fdf9df5b
hw/core: Add CPUClass.get_pc
...
Populate this new method for all targets. Always match
the result that would be given by cpu_get_tb_cpu_state,
as we will want these values to correspond in the logs.
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com >
Reviewed-by: Alex Bennée <alex.bennee@linaro.org >
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk > (target/sparc)
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
---
Cc: Eduardo Habkost <eduardo@habkost.net > (supporter:Machine core)
Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com > (supporter:Machine core)
Cc: "Philippe Mathieu-Daudé" <f4bug@amsat.org > (reviewer:Machine core)
Cc: Yanan Wang <wangyanan55@huawei.com > (reviewer:Machine core)
Cc: Michael Rolnik <mrolnik@gmail.com > (maintainer:AVR TCG CPUs)
Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com > (maintainer:CRIS TCG CPUs)
Cc: Taylor Simpson <tsimpson@quicinc.com > (supporter:Hexagon TCG CPUs)
Cc: Song Gao <gaosong@loongson.cn > (maintainer:LoongArch TCG CPUs)
Cc: Xiaojuan Yang <yangxiaojuan@loongson.cn > (maintainer:LoongArch TCG CPUs)
Cc: Laurent Vivier <laurent@vivier.eu > (maintainer:M68K TCG CPUs)
Cc: Jiaxun Yang <jiaxun.yang@flygoat.com > (reviewer:MIPS TCG CPUs)
Cc: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com > (reviewer:MIPS TCG CPUs)
Cc: Chris Wulff <crwulff@gmail.com > (maintainer:NiosII TCG CPUs)
Cc: Marek Vasut <marex@denx.de > (maintainer:NiosII TCG CPUs)
Cc: Stafford Horne <shorne@gmail.com > (odd fixer:OpenRISC TCG CPUs)
Cc: Yoshinori Sato <ysato@users.sourceforge.jp > (reviewer:RENESAS RX CPUs)
Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk > (maintainer:SPARC TCG CPUs)
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de > (maintainer:TriCore TCG CPUs)
Cc: Max Filippov <jcmvbkbc@gmail.com > (maintainer:Xtensa TCG CPUs)
Cc: qemu-arm@nongnu.org (open list:ARM TCG CPUs)
Cc: qemu-ppc@nongnu.org (open list:PowerPC TCG CPUs)
Cc: qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs)
Cc: qemu-s390x@nongnu.org (open list:S390 TCG CPUs)
2022-10-04 12:13:12 -07:00
adb5974dcc
target/avr: Drop avr_cpu_memory_rw_debug()
...
CPUClass::memory_rw_debug() holds a callback for GDB memory access.
If not provided, cpu_memory_rw_debug() is used by the GDB stub.
Drop avr_cpu_memory_rw_debug() which does nothing special.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com >
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Message-Id: <20220322095004.70682-1-bmeng.cn@gmail.com >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2022-06-20 13:11:36 -07:00
d2470cf0e9
target/avr: Remove pointless use of CONFIG_USER_ONLY definition
...
Commit f1c671f96c7827168471richard.henderson@linaro.org >
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-By: Warner Losh <imp@bsdimp.com >
Message-Id: <20210911165434.531552-2-f4bug@amsat.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2021-09-14 12:00:20 -07:00
e64cb6c231
target/avr: Implement gdb_adjust_breakpoint
...
Ensure at registration that all breakpoints are in
code space, not data space.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2021-07-21 07:47:05 -10:00
119065574d
hw/core: Constify TCGCPUOps
...
We no longer have any runtime modifications to this struct,
so declare them all const.
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-ID: <20210227232519.222663-3-richard.henderson@linaro.org >
2021-05-26 15:33:59 -07:00
08928c6d0d
cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOps
...
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20210517105140.1062037-21-f4bug@amsat.org >
[rth: Drop declaration movement from target/*/cpu.h]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2021-05-26 15:33:59 -07:00
8b80bd28a5
cpu: Introduce SysemuCPUOps structure
...
Introduce a structure to hold handler specific to sysemu.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20210517105140.1062037-15-f4bug@amsat.org >
[rth: Squash "restrict hw/core/sysemu-cpu-ops.h" patch]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2021-05-26 15:33:59 -07:00
c2cf139d9c
cpu: Move AVR target vmsd field from CPUClass to DeviceClass
...
See rationale in previous commit. Targets should use the vmsd field
of DeviceClass, not CPUClass. As migration is not important on the
AVR target, break the migration compatibility and set the DeviceClass
vmsd field. To feel safer, increment the vmstate version.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Message-Id: <20210517105140.1062037-14-f4bug@amsat.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2021-05-26 15:33:59 -07:00
744c72a837
cpu: Rename CPUClass vmsd -> legacy_vmsd
...
Quoting Peter Maydell [*]:
There are two ways to handle migration for
a CPU object:
(1) like any other device, so it has a dc->vmsd that covers
migration for the whole object. As usual for objects that are a
subclass of a parent that has state, the first entry in the
VMStateDescription field list is VMSTATE_CPU(), which migrates
the cpu_common fields, followed by whatever the CPU's own migration
fields are.
(2) a backwards-compatible mechanism for CPUs that were
originally migrated using manual "write fields to the migration
stream structures". The on-the-wire migration format
for those is based on the 'env' pointer (which isn't a QOM object),
and the cpu_common part of the migration data is elsewhere.
cpu_exec_realizefn() handles both possibilities:
* for type 1, dc->vmsd is set and cc->vmsd is not,
so cpu_exec_realizefn() does nothing, and the standard
"register dc->vmsd for a device" code does everything needed
* for type 2, dc->vmsd is NULL and so we register the
vmstate_cpu_common directly to handle the cpu-common fields,
and the cc->vmsd to handle the per-CPU stuff
You can't change a CPU from one type to the other without breaking
migration compatibility, which is why some guest architectures
are stuck on the cc->vmsd form. New targets should use dc->vmsd.
To avoid new targets to start using type (2), rename cc->vmsd as
cc->legacy_vmsd. The correct field to implement is dc->vmsd (the
DeviceClass one).
See also commit b170fce3ddhttps://www.mail-archive.com/qemu-devel@nongnu.org/msg800849.html
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Cc: Peter Maydell <peter.maydell@linaro.org >
Message-Id: <20210517105140.1062037-13-f4bug@amsat.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2021-05-26 15:33:59 -07:00
27aefd66d6
target/avr/cpu: Use device_class_set_parent_realize()
...
Change generated automatically using the Coccinelle
patch included in commit bf85388169f4bug@amsat.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20210201080348.438095-1-f4bug@amsat.org >
Signed-off-by: Laurent Vivier <laurent@vivier.eu >
2021-02-20 12:36:19 +01:00
7827168471
cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass
...
we cannot in principle make the TCG Operations field definitions
conditional on CONFIG_TCG in code that is included by both common_ss
and specific_ss modules.
Therefore, what we can do safely to restrict the TCG fields to TCG-only
builds, is to move all tcg cpu operations into a separate header file,
which is only included by TCG, target-specific code.
This leaves just a NULL pointer in the cpu.h for the non-TCG builds.
This also tidies up the code in all targets a bit, having all TCG cpu
operations neatly contained by a dedicated data struct.
Signed-off-by: Claudio Fontana <cfontana@suse.de >
Message-Id: <20210204163931.7358-16-cfontana@suse.de >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2021-02-05 10:24:15 -10:00
0545608056
cpu: move cc->do_interrupt to tcg_ops
...
Signed-off-by: Claudio Fontana <cfontana@suse.de >
Reviewed-by: Alex Bennée <alex.bennee@linaro.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20210204163931.7358-10-cfontana@suse.de >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2021-02-05 10:24:14 -10:00
e124536f37
cpu: Move tlb_fill to tcg_ops
...
[claudio: wrapped target code in CONFIG_TCG]
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com >
Signed-off-by: Claudio Fontana <cfontana@suse.de >
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com >
Reviewed-by: Alex Bennée <alex.bennee@linaro.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20210204163931.7358-7-cfontana@suse.de >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2021-02-05 10:24:14 -10:00
48c1a3e303
cpu: Move cpu_exec_* to tcg_ops
...
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com >
[claudio: wrapped target code in CONFIG_TCG]
Signed-off-by: Claudio Fontana <cfontana@suse.de >
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com >
Reviewed-by: Alex Bennée <alex.bennee@linaro.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20210204163931.7358-6-cfontana@suse.de >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2021-02-05 10:24:14 -10:00
ec62595bab
cpu: Move synchronize_from_tb() to tcg_ops
...
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com >
[claudio: wrapped target code in CONFIG_TCG, reworded comments]
Signed-off-by: Claudio Fontana <cfontana@suse.de >
Reviewed-by: Alex Bennée <alex.bennee@linaro.org >
Message-Id: <20210204163931.7358-5-cfontana@suse.de >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2021-02-05 10:24:14 -10:00
e9e51b7154
cpu: Introduce TCGCpuOperations struct
...
The TCG-specific CPU methods will be moved to a separate struct,
to make it easier to move accel-specific code outside generic CPU
code in the future. Start by moving tcg_initialize().
The new CPUClass.tcg_opts field may eventually become a pointer,
but keep it an embedded struct for now, to make code conversion
easier.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com >
[claudio: move TCGCpuOperations inside include/hw/core/cpu.h]
Reviewed-by: Alex Bennée <alex.bennee@linaro.org >
Message-Id: <20210204163931.7358-2-cfontana@suse.de >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2021-02-05 10:24:14 -10:00
04a37d4ca4
tcg: Make tb arg to synchronize_from_tb const
...
There is nothing within the translators that ought to be
changing the TranslationBlock data, so make it const.
This does not actually use the read-only copy of the
data structure that exists within the rx region.
Reviewed-by: Joelle van Dyne <j@getutm.app >
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2021-01-07 05:09:41 -10:00
2e34e622c2
target/avr/cpu: Fix $PC displayed address
...
$PC is 16-bit wide. Other registers display addresses on a byte
granularity.
To have a coherent ouput, display $PC using byte granularity too.
Reviewed-by: Thomas Huth <huth@tuxfamily.org >
Reviewed-by: Alex Bennée <alex.bennee@linaro.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Message-Id: <20200707070021.10031-3-f4bug@amsat.org >
2020-07-11 11:02:05 +02:00
a291bc851d
target/avr/cpu: Drop tlb_flush() in avr_cpu_reset()
...
Since commit 1f5c00cfdbhuth@tuxfamily.org >
Reviewed-by: Alex Bennée <alex.bennee@linaro.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Message-Id: <20200707070021.10031-2-f4bug@amsat.org >
2020-07-11 11:02:05 +02:00
9d8caa67a2
target/avr: Add support for disassembling via option '-d in_asm'
...
Provide function disassembles executed instruction when '-d in_asm' is
provided.
Example:
$ qemu-system-avr -bios free-rtos/Demo/AVR_ATMega2560_GCC/demo.elf -d in_asm
...
IN:
0x0000014a: CALL 0x3808
IN: main
0x00003808: CALL 0x4b4
IN: vParTestInitialise
0x000004b4: LDI r24, 255
0x000004b6: STS r24, 0
0x000004b8: MULS r16, r20
0x000004ba: OUT $1, r24
0x000004bc: LDS r24, 0
0x000004be: MULS r16, r20
0x000004c0: OUT $2, r24
0x000004c2: RET
...
Suggested-by: Richard Henderson <richard.henderson@linaro.org >
Suggested-by: Philippe Mathieu-Daudé <philmd@redhat.com >
Suggested-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com >
Signed-off-by: Michael Rolnik <mrolnik@gmail.com >
[rth: Fix spacing and const mnemonic arrays]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com >
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com >
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com >
Signed-off-by: Thomas Huth <huth@tuxfamily.org >
Message-Id: <20200705140315.260514-19-huth@tuxfamily.org >
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
2020-07-11 11:02:05 +02:00
669d27e2f5
target/avr: Add definitions of AVR core types
...
AVR core types are:
- avr5
- avr51
- avr6
Each core type covers multiple AVR MCUs, mentioned in the comments
before definition of particular AVR core type (part of this patch).
AVR core type defines shared features that are valid for all AVR
MCUs belonging in that type.
[AM: Split a larger AVR introduction patch into logical units]
Suggested-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com >
Co-developed-by: Michael Rolnik <mrolnik@gmail.com >
Co-developed-by: Sarah Harris <S.E.Harris@kent.ac.uk >
Signed-off-by: Michael Rolnik <mrolnik@gmail.com >
Signed-off-by: Sarah Harris <S.E.Harris@kent.ac.uk >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com >
Acked-by: Igor Mammedov <imammedo@redhat.com >
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com >
Signed-off-by: Thomas Huth <huth@tuxfamily.org >
Message-Id: <20200705140315.260514-9-huth@tuxfamily.org >
[PMD: Only include reviewed cores: avr5/avr51/avr6]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
2020-07-10 17:58:32 +02:00
12b3540547
target/avr: CPU class: Add GDB support
...
This includes GDB hooks for reading from wnd wrtiting to AVR
registers, and xml register definition file as well.
[AM: Split a larger AVR introduction patch into logical units]
Suggested-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com >
Co-developed-by: Michael Rolnik <mrolnik@gmail.com >
Co-developed-by: Sarah Harris <S.E.Harris@kent.ac.uk >
Signed-off-by: Michael Rolnik <mrolnik@gmail.com >
Signed-off-by: Sarah Harris <S.E.Harris@kent.ac.uk >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com >
Acked-by: Igor Mammedov <imammedo@redhat.com >
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com >
[thuth: Fixed avr_cpu_gdb_read_register() parameter]
Signed-off-by: Thomas Huth <huth@tuxfamily.org >
Message-Id: <20200705140315.260514-7-huth@tuxfamily.org >
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
2020-07-10 17:58:32 +02:00
3fa28dd6cf
target/avr: CPU class: Add migration support
...
Add migration-related functions of AVR CPU class object.
[AM: Split a larger AVR introduction patch into logical units]
Suggested-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com >
Co-developed-by: Michael Rolnik <mrolnik@gmail.com >
Co-developed-by: Sarah Harris <S.E.Harris@kent.ac.uk >
Signed-off-by: Michael Rolnik <mrolnik@gmail.com >
Signed-off-by: Sarah Harris <S.E.Harris@kent.ac.uk >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com >
Acked-by: Igor Mammedov <imammedo@redhat.com >
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com >
Signed-off-by: Thomas Huth <huth@tuxfamily.org >
Message-Id: <20200705140315.260514-6-huth@tuxfamily.org >
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
2020-07-10 17:58:32 +02:00
e2a2b0b918
target/avr: CPU class: Add memory management support
...
This patch introduces three memory-management-related functions
that will become part of AVR CPU class object.
[AM: Split a larger AVR introduction patch into logical units]
Suggested-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com >
Co-developed-by: Michael Rolnik <mrolnik@gmail.com >
Co-developed-by: Sarah Harris <S.E.Harris@kent.ac.uk >
Signed-off-by: Michael Rolnik <mrolnik@gmail.com >
Signed-off-by: Sarah Harris <S.E.Harris@kent.ac.uk >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com >
Acked-by: Igor Mammedov <imammedo@redhat.com >
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com >
Signed-off-by: Thomas Huth <huth@tuxfamily.org >
Message-Id: <20200705140315.260514-5-huth@tuxfamily.org >
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
2020-07-10 17:58:32 +02:00
7ccda78ff3
target/avr: CPU class: Add interrupt handling support
...
This patch introduces functions avr_cpu_do_interrupt() and
avr_cpu_exec_interrupt() that are part of AVR CPU class object.
[AM: Split a larger AVR introduction patch into logical units]
Suggested-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com >
Co-developed-by: Michael Rolnik <mrolnik@gmail.com >
Co-developed-by: Sarah Harris <S.E.Harris@kent.ac.uk >
Signed-off-by: Michael Rolnik <mrolnik@gmail.com >
Signed-off-by: Sarah Harris <S.E.Harris@kent.ac.uk >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com >
Acked-by: Igor Mammedov <imammedo@redhat.com >
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com >
Signed-off-by: Thomas Huth <huth@tuxfamily.org >
Message-Id: <20200705140315.260514-4-huth@tuxfamily.org >
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
2020-07-10 17:58:32 +02:00
f1c671f96c
target/avr: Introduce basic CPU class object
...
This patch introduces AVR CPU class object and its basic elements
and functions.
[AM: Split a larger AVR introduction patch into logical units]
Suggested-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com >
Co-developed-by: Michael Rolnik <mrolnik@gmail.com >
Co-developed-by: Sarah Harris <S.E.Harris@kent.ac.uk >
Signed-off-by: Michael Rolnik <mrolnik@gmail.com >
Signed-off-by: Sarah Harris <S.E.Harris@kent.ac.uk >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com >
Acked-by: Igor Mammedov <imammedo@redhat.com >
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com >
[thuth: Adjusted reset and parent_reset handling]
Signed-off-by: Thomas Huth <huth@tuxfamily.org >
Message-Id: <20200705140315.260514-3-huth@tuxfamily.org >
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
2020-07-10 17:58:32 +02:00
