89854803ce
RISC-V: Remove EM_RISCV ELF_MACHINE indirection
...
Pointless indirection. Other ports use EM_ constants directly.
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu >
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de >
Signed-off-by: Michael Clark <mjc@sifive.com >
Signed-off-by: Palmer Dabbelt <palmer@sifive.com >
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
2018-05-06 10:39:38 +12:00
42b3a4b7cc
RISC-V: Remove unused class definitions
...
Removes a whole lot of unnecessary boilerplate code. Machines
don't need to be objects. The expansion of the SOC object model
for the RISC-V machines will happen in the future as SiFive
plans to add their FE310 and FU540 SOCs to QEMU. However, it
seems that this present boilerplate is complete unnecessary.
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu >
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de >
Signed-off-by: Michael Clark <mjc@sifive.com >
Signed-off-by: Palmer Dabbelt <palmer@sifive.com >
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
2018-05-06 10:39:38 +12:00
b7938980fb
RISC-V: Remove identity_translate from load_elf
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When load_elf is called with NULL as an argument to the
address translate callback, it does an identity translation.
This commit removes the redundant identity_translate callback.
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu >
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de >
Signed-off-by: Michael Clark <mjc@sifive.com >
Signed-off-by: Palmer Dabbelt <palmer@sifive.com >
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
2018-05-06 10:39:38 +12:00
6b01e3277e
RISC-V: Use ROM base address and size from memmap
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Another case of replacing hard coded constants, this time
referring to the definition in the virt machine's memmap.
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu >
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de >
Signed-off-by: Michael Clark <mjc@sifive.com >
Signed-off-by: Palmer Dabbelt <palmer@sifive.com >
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
2018-05-06 10:39:38 +12:00
77ff5bba31
RISC-V: Make virt board description match spike
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This makes 'qemu-system-riscv64 -machine help' output more tidy
and consistent.
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu >
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de >
Signed-off-by: Michael Clark <mjc@sifive.com >
Signed-off-by: Palmer Dabbelt <palmer@sifive.com >
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
2018-05-06 10:39:38 +12:00
2a8756ed7d
RISC-V: Replace hardcoded constants with enum values
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The RISC-V device-tree code has a number of hard-coded
constants and this change moves them into header enums.
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu >
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de >
Signed-off-by: Michael Clark <mjc@sifive.com >
Signed-off-by: Palmer Dabbelt <palmer@sifive.com >
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
2018-05-06 10:39:38 +12:00
9bca0edb28
Change references to serial_hds[] to serial_hd()
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Change all the uses of serial_hds[] to go via the new
serial_hd() function. Code change produced with:
find hw -name '*.[ch]' | xargs sed -i -e 's/serial_hds\[\([^]]*\)\]/serial_hd(\1)/g'
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
Reviewed-by: Thomas Huth <thuth@redhat.com >
Message-id: 20180420145249.32435-8-peter.maydell@linaro.org
2018-04-26 13:57:00 +01:00
04331d0b56
RISC-V VirtIO Machine
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RISC-V machine with device-tree, 16550a UART and VirtIO MMIO.
The following machine is implemented:
- 'virt'; CLINT, PLIC, 16550A UART, VirtIO MMIO, device-tree
Acked-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: Palmer Dabbelt <palmer@sifive.com >
Signed-off-by: Michael Clark <mjc@sifive.com >
2018-03-07 08:30:28 +13:00
