cc37d98bfb
*: Add missing includes of qemu/error-report.h
...
This had been pulled in via qemu/plugin.h from hw/core/cpu.h,
but that will be removed.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org >
Message-Id: <20230310195252.210956-5-richard.henderson@linaro.org >
[AJB: add various additional cases shown by CI]
Signed-off-by: Alex Bennée <alex.bennee@linaro.org >
Message-Id: <20230315174331.2959-15-alex.bennee@linaro.org >
Reviewed-by: Emilio Cota <cota@braap.org >
2023-03-22 15:06:57 +00:00
ebfd392893
hw/riscv/virt: virt-acpi-build.c: Add RHCT Table
...
RISC-V ACPI platforms need to provide RISC-V Hart Capabilities
Table (RHCT). Add this to the ACPI tables.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com >
Reviewed-by: Andrew Jones <ajones@ventanamicro.com >
Message-ID: <20230302091212.999767-7-sunilvl@ventanamicro.com >
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com >
2023-03-06 11:35:06 -08:00
6cc40ea211
hw/riscv/virt: virt-acpi-build.c: Add RINTC in MADT
...
Add Multiple APIC Description Table (MADT) with the
RINTC structure for each cpu.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com >
Acked-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Andrew Jones <ajones@ventanamicro.com >
Message-ID: <20230302091212.999767-6-sunilvl@ventanamicro.com >
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com >
2023-03-06 11:35:05 -08:00
7da2fb240f
hw/riscv/virt: Enable basic ACPI infrastructure
...
Add basic ACPI infrastructure for RISC-V with below tables.
1) DSDT with below basic objects
- CPUs
- fw_cfg
2) FADT revision 6 with HW_REDUCED flag
3) XSDT
4) RSDP
Add this functionality in a new file virt-acpi-build.c and enable
building this infrastructure.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com >
Reviewed-by: Andrew Jones <ajones@ventanamicro.com >
Message-ID: <20230302091212.999767-5-sunilvl@ventanamicro.com >
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com >
2023-03-06 11:35:04 -08:00
