6efbac908f
aspeed: add the definitions for the AST2400 A1 SoC
...
There is not much differences with the A0 revision apart from the DDR
calibration.
Signed-off-by: Cédric Le Goater <clg@kaod.org >
Reviewed-by: Joel Stanley <joel@jms.id.au >
Reviewed-by: Andrew Jeffery <andrew@aj.id.au >
Message-id: 1480434248-27138-10-git-send-email-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2016-12-27 14:59:28 +00:00
c6c7cfb01a
aspeed: add a ram_size property to the memory controller
...
Configure the size of the RAM of the SOC using a property to propagate
the value down to the memory controller from the board level.
Signed-off-by: Cédric Le Goater <clg@kaod.org >
Reviewed-by: Andrew Jeffery <andrew@aj.id.au >
Message-id: 1473438177-26079-14-git-send-email-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2016-09-22 18:13:06 +01:00
b2fd45458d
aspeed: use error_report instead of LOG_GUEST_ERROR
...
Also change the default value used in case of an error. The minimum
size is a bit severe, so let's just use an average RAM size.
Signed-off-by: Cédric Le Goater <clg@kaod.org >
Message-id: 1473438177-26079-13-git-send-email-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2016-09-22 18:13:06 +01:00
3755f9e316
aspeed: calculate the RAM size bits at realize time
...
There is no need to do this at each reset as the RAM size will not
change.
Signed-off-by: Cédric Le Goater <clg@kaod.org >
Reviewed-by: Andrew Jeffery <andrew@aj.id.au >
Message-id: 1473438177-26079-12-git-send-email-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2016-09-22 18:13:06 +01:00
365aff1eaa
aspeed: add a ast2500 SoC and support to the SCU and SDMC controllers
...
Based on previous work done by Andrew Jeffery <andrew@aj.id.au >.
Signed-off-by: Cédric Le Goater <clg@kaod.org >
Reviewed-by: Andrew Jeffery <andrew@aj.id.au >
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Message-id: 1473438177-26079-9-git-send-email-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2016-09-22 18:13:05 +01:00
c2da8a8b90
ast2400: add a memory controller device model
...
The uboot in the previous release of the SDK was using a hardcoded
value for memory size. This is not true anymore, the value is now
retrieved from the memory controller.
Below is a model for this device, only supporting unlock and
configuration. Without it, we endup running a guest with 64MB, which
is a bit low nowdays. It uses a 'silicon-rev' property and ram_size to
build a default value. Some bits should be linked to SCU strapping
registers but it seems a bit complex to add for the current need.
The model is ready for the AST2500 SOC.
Signed-off-by: Cédric Le Goater <clg@kaod.org >
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2016-09-06 19:52:17 +01:00
