3 Commits

Author	SHA1	Message	Date
Alistair Francis	651cd8b7e1	hw/riscv/sifive_e: Create a SiFive E SoC object ... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Michael Clark <mjc@sifive.com>	2018-07-05 15:24:25 -07:00
Michael Clark	42b3a4b7cc	RISC-V: Remove unused class definitions ... Removes a whole lot of unnecessary boilerplate code. Machines don't need to be objects. The expansion of the SOC object model for the RISC-V machines will happen in the future as SiFive plans to add their FE310 and FU540 SOCs to QEMU. However, it seems that this present boilerplate is complete unnecessary. Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>	2018-05-06 10:39:38 +12:00
Michael Clark	eb637edb12	SiFive Freedom E Series RISC-V Machine ... This provides a RISC-V Board compatible with the the SiFive Freedom E SDK. The following machine is implemented: - 'sifive_e'; CLINT, PLIC, UART, AON, GPIO, QSPI, PWM Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Sagar Karandikar <sagark@eecs.berkeley.edu> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Michael Clark <mjc@sifive.com>	2018-03-07 08:30:28 +13:00