04965bca4e
xlnx-zynqmp: Connect the ZynqMP GDMA and ADMA
...
The ZynqMP contains two instances of a generic DMA, the GDMA, located in the
FPD (full power domain), and the ADMA, located in LPD (low power domain). This
patch adds these two DMAs to the ZynqMP board.
Signed-off-by: Francisco Iglesias <frasse.iglesias@gmail.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com >
Message-id: 20180503214201.29082-3-frasse.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2018-05-18 17:48:07 +01:00
08b2f15e67
xlnx-zynqmp: Connect the RTC device
...
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com >
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2018-03-02 10:45:35 +00:00
0ab7bbc75b
xlnx-zynqmp: Connect the IPI device to the ZynqMP SoC
...
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com >
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com >
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com >
2018-01-26 11:09:09 +01:00
babc1f3009
xlnx-zcu102: Add support for the ZynqMP QSPI
...
Add support for the ZynqMP QSPI (consisting of the Generic QSPI and Legacy
QSPI) and connect Numonyx n25q512a11 flashes to it.
Signed-off-by: Francisco Iglesias <frasse.iglesias@gmail.com >
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com >
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com >
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com >
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Message-id: 20171126231634.9531-14-frasse.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2017-12-13 17:59:22 +00:00
1946809ece
xlnx-zcu102: Add a machine level virtualization property
...
Add a machine level virtualization property. This defaults to false and can be
set to true using this machine command line argument:
-machine xlnx-zcu102,virtualization=on
This follows what the ARM virt machine does.
This property only applies to the ZCU102 machine. The EP108 machine does
not have this property.
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com >
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com >
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2017-09-14 18:43:18 +01:00
b93dbcdd59
arm: xlnx-zynqmp: Add xlnx-dp and xlnx-dpdma
...
This adds the DP and the DPDMA to the Zynq MP platform.
Signed-off-by: KONRAD Frederic <fred.konrad@greensocs.com >
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com >
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com >
Tested-By: Hyun Kwon <hyun.kwon@xilinx.com >
Message-id: 1465833014-21982-10-git-send-email-fred.konrad@greensocs.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2016-06-14 16:01:03 +01:00
6ed92b14f6
xlnx-zynqmp: Make the RPU subsystem optional
...
The way we currently model the RPU subsystem is of quite
limited use. In addition to that, it causes problems for
KVM and for GDB debugging.
Make the RPU optional by adding a has_rpu property and
default to having it disabled.
This changes the default setup from having the RPU to not
longer having it.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com >
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com >
Message-id: 1464173555-12800-3-git-send-email-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2016-06-06 16:59:29 +01:00
37d42473d1
xlnx-zynqmp: Add a secure prop to en/disable ARM Security Extensions
...
Add a secure prop to en/disable ARM Security Extensions.
This is particularly useful for KVM runs.
Default to disabled to match the behavior of KVM.
This changes the default setup from having the ARM Security
Extensions to not longer having them.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com >
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com >
Message-id: 1464173555-12800-2-git-send-email-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2016-06-06 16:59:29 +01:00
02d07eb494
xlnx-zynqmp: Connect the SPI devices
...
Connect the Xilinx SPI devices to the ZynqMP model.
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com >
Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com >
[ PC changes
* Use QOM alias for bus connectivity on SoC level
]
Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com >
[PMM: free the g_strdup_printf() string when finished with it]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2016-01-21 14:15:03 +00:00
dc3b89ef87
xlnx-zynqmp: Add support for high DDR memory regions
...
The Xilinx ZynqMP SoC and EP108 board supports three memory regions:
- A 2GB region starting at 0
- A 32GB region starting at 32GB
- A 256GB region starting at 768GB
This patch adds support for the first two memory regions, which is
automatically created based on the size specified by the QEMU memory
command line argument.
On hardware the physical memory region is one continuous region, it is then
mapped into the three different regions by the DDRC. As we don't model the
DDRC this is done at startup by QEMU. The board creates the memory region and
then passes that memory region to the SoC. The SoC then maps the memory
regions.
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com >
Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com >
Message-id: a1e47db941d65733724a300fcd98b74fbeeaaf22.1452637205.git.alistair.francis@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2016-01-15 14:34:54 +00:00
33108e9f33
target-arm: xlnx-zynqmp: Add sdhci support.
...
Add two SYSBUS_SDHCI devices for xlnx-zynqmp
Signed-off-by: Sai Pavan Boddu <saipava@xilinx.com >
Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com >
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com >
2015-10-29 17:59:27 +00:00
52c16b458a
arm: xlnx-zynqmp: Fix up GIC region size
...
The GIC in ZynqMP cover a 64K address space, however the actual
registers are decoded within a 4K address space and mirrored at the 4K
boundaries. This change fixes the defined size for these regions as it
was set to 0x4000/16K incorrectly.
Signed-off-by: Nathan Rossi <nathan@nathanrossi.com >
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com >
Message-id: 1441719672-25296-1-git-send-email-nathan@nathanrossi.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-09-14 14:39:47 +01:00
6fdf3282d1
xlnx-zynqmp: Connect the sysbus AHCI to ZynqMP
...
Connect the Sysbus AHCI device to ZynqMP.
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com >
Reviewed-by: Sai Pavan Boddu <saipava@xilinx.com >
[PMM: removed unnecessary brackets in error_propagate call]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-09-08 17:38:45 +01:00
6675d71915
xlnx-zynqmp: Connect the four OCM banks
...
The Xilinx EP108 has four separate OCM banks which are located
adjacent to each other. This patch adds the four banks to
the ZynqMP SoC.
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com >
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com >
Message-id: afa6ba31163a5d541a0bef4b0dc11f2597e0c495.1436813543.git.alistair.francis@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-08-25 15:45:06 +01:00
b58850e79d
arm: xlnx-zynqmp: Add 2xCortexR5 CPUs
...
Add the 2xCortexR5 CPUs to zynqmp board. They are powered off on reset
(this is true of real hardware) by default or selectable as the boot
processor.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com >
Message-id: da34128c73ca13fc4f8c3293e1a33d1e1e345655.1434501320.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-06-19 14:17:45 +01:00
6396a193d3
arm: xlnx-zynqmp: Add boot-cpu property
...
Add a string property that specifies the primary boot cpu. All CPUs
except the one selected will start-powered-off. This allows for elf
boots on any CPU, which prepares support for booting R5 elfs directly
on the R5 processors.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com >
Message-id: 53331c00d80c7ce9c6a83712348773f1b38fae2b.1434501320.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-06-19 14:17:45 +01:00
2e5577bc55
arm: xlnx-zynqmp: Preface CPU variables with "apu"
...
The CPUs currently supported by zynqmp are the APU (application
processing unit) CPUs. There are other CPUs in Zynqmp so unqualified
"cpus" in ambiguous. Preface the variables with "APU" accordingly, to
prepare support adding the RPU (realtime processing unit) processors.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com >
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com >
Message-id: ce32287fc365aea898465e981da3546a227e0811.1434501320.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-06-19 14:17:45 +01:00
3bade2a9e6
arm: xlnx-zynqmp: Add UART support
...
There are 2x Cadence UARTs in Zynq MP. Add them.
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com >
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Tested-by: Alistair Francis <alistair.francis@xilinx.com >
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com >
Message-id: e30795536f77599fabc1052278d846ccd52322e2.1431381507.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-05-18 16:41:13 +01:00
14ca2e462e
arm: xlnx-zynqmp: Add GEM support
...
There are 4x Cadence GEMs in ZynqMP. Add them.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Tested-by: Alistair Francis <alistair.francis@xilinx.com >
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com >
Message-id: 7d3e68e5495d145255f0ee567046415e3a26d67e.1431381507.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-05-18 16:41:11 +01:00
7729e1f4b3
arm: xlnx-zynqmp: Add GIC
...
Add the GIC and connect IRQ outputs to the CPUs. The GIC regions are
under-decoded through a 64k address region so implement aliases
accordingly.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com >
Message-id: 5853189965728d676106d9e94e76b9bb87981cb5.1431381507.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-05-18 16:41:09 +01:00
f0a902f764
arm: Introduce Xilinx ZynqMP SoC
...
With quad Cortex-A53 CPUs.
Use SMC PSCI, with the standard policy of secondaries starting in
power-off.
Tested-by: Alistair Francis <alistair.francis@xilinx.com >
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com >
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com >
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com >
Message-id: a16202a6c7b79e446e5289d38cb18d2ee4b897a0.1431381507.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-05-18 16:41:09 +01:00
