d419890c04
hw/intc/arm_gicv3: fix an extra left-shift when reading IPRIORITYR
...
When either GICD_IPRIORITYR or GICR_IPRIORITYR is read as a 32-bit
register, the post left-shift operator in the for loop causes an
extra shift after the least significant byte has been placed.
The 32-bit value actually returned is therefore the expected value
shifted left by 8 bits.
Signed-off-by: Amol Surati <suratiamol@gmail.com >
Message-id: 20180614054857.26248-1-suratiamol@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2018-06-22 13:28:34 +01:00
f1945632b4
hw/intc/arm_gicv3: Make reserved register addresses RAZ/WI
...
The GICv3 specification says that reserved register addresses
should RAZ/WI. This means we need to return MEMTX_OK, not MEMTX_ERROR,
because now that we support generating external aborts the
latter will cause an abort on new board models.
Cc: qemu-stable@nongnu.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
Message-id: 1513183941-24300-2-git-send-email-peter.maydell@linaro.org
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com >
2018-01-11 13:25:40 +00:00
b1e3493b25
hw/intc/arm_gicv3: Fix compilation with simple trace backend
...
Fix missing includes of qemu/log.h, which broke compilation with the
simple trace backend (the default backend pulls in log.h implicitly
via trace.h).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
Reviewed-by: Sergey Fedorov <sergey.fedorov@linaro.org >
Tested-by: Sergey Fedorov <sergey.fedorov@linaro.org >
Message-id: 1466416634-9798-1-git-send-email-peter.maydell@linaro.org
2016-06-20 11:35:15 +01:00
c84428b33f
hw/intc/arm_gicv3: Implement gicv3_set_irq()
...
Implement the code which updates the GIC state when an interrupt
input into the GIC is asserted.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org >
Tested-by: Shannon Zhao <shannon.zhao@linaro.org >
Message-id: 1465915112-29272-15-git-send-email-peter.maydell@linaro.org
2016-06-17 15:23:51 +01:00
e52af51340
hw/intc/arm_gicv3: Implement GICv3 distributor registers
...
Implement the distributor registers of a GICv3.
Signed-off-by: Shlomo Pongratz <shlomo.pongratz@huawei.com >
Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org >
Tested-by: Shannon Zhao <shannon.zhao@linaro.org >
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
Message-id: 1465915112-29272-12-git-send-email-peter.maydell@linaro.org
[PMM: significantly overhauled/rewritten:
* use the new bitmap data structures
* restructure register read/write to handle different width accesses
natively, since almost all registers are 32-bit only, rather
than implementing everything as byte accesses
* implemented security extension support
]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2016-06-17 15:23:51 +01:00
