50fba816cd
RISC-V: Add support for the Zifencei extension
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fence.i has been split out of the base ISA as part of the ratification
process. This patch adds a Zifencei argument, which disables the
fence.i instruction.
Signed-off-by: Palmer Dabbelt <palmer@sifive.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
2019-06-25 22:31:21 -07:00
598aa1160c
target/riscv: Split gen_arith_imm into functional and temp
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The tcg_gen_fooi_tl functions have some immediate constant
folding built in, which match up with some of the riscv asm
builtin macros, like mv and not.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Palmer Dabbelt <palmer@sifive.com >
Signed-off-by: Palmer Dabbelt <palmer@sifive.com >
2019-05-24 12:09:23 -07:00
c2cfb97c01
target/riscv: Use pattern groups in insn16.decode
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This eliminates about half of the complicated decode
bits within insn_trans/trans_rvc.inc.c.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Palmer Dabbelt <palmer@sifive.com >
Signed-off-by: Palmer Dabbelt <palmer@sifive.com >
2019-05-24 12:09:22 -07:00
6e2716d8ca
RISC-V: fix single stepping over ret and other branching instructions
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This patch introduces wrappers around the tcg_gen_exit_tb() and
tcg_gen_lookup_and_goto_ptr() functions that handle single stepping,
i.e. call gen_exception_debug() when single stepping is enabled.
Theses functions are then used instead of the originals, bringing single
stepping handling in places where it was previously ignored such as jalr
and system branch instructions (ecall, mret, sret, etc.).
Signed-off-by: Fabien Chouteau <chouteau@adacore.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Palmer Dabbelt <palmer@sifive.com >
2019-05-24 12:09:22 -07:00
8dc9e8a8b0
target/riscv: Rename trans_arith to gen_arith
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Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de >
2019-03-13 10:40:50 +01:00
34446e8458
target/riscv: Remove shift and slt insn manual decoding
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Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de >
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de >
2019-03-13 10:40:50 +01:00
f2ab172867
target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
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manual decoding in gen_arith() is not necessary with decodetree. For now
the function is called trans_arith as the original gen_arith still
exists. The former will be renamed to gen_arith as soon as the old
gen_arith can be removed.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de >
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de >
2019-03-13 10:40:50 +01:00
7a50d3e2ae
target/riscv: Move gen_arith_imm() decoding into trans_* functions
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gen_arith_imm() does a lot of decoding manually, which was hard to read
in case of the shift instructions and is not necessary anymore with
decodetree.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de >
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de >
2019-03-13 10:40:50 +01:00
bce8a342a1
target/riscv: Remove manual decoding from gen_store()
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With decodetree we don't need to convert RISC-V opcodes into to MemOps
as the old gen_store() did.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de >
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de >
2019-03-13 10:40:50 +01:00
98898b20e9
target/riscv: Remove manual decoding from gen_load()
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With decodetree we don't need to convert RISC-V opcodes into to MemOps
as the old gen_load() did.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de >
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de >
2019-03-13 10:40:50 +01:00
090cc2c898
target/riscv: Remove manual decoding from gen_branch()
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We now utilizes argument-sets of decodetree such that no manual
decoding is necessary.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de >
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de >
2019-03-13 10:40:50 +01:00
9e92c57d83
target/riscv: Remove gen_jalr()
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trans_jalr() is the only caller, so move the code into trans_jalr().
Acked-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de >
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de >
2019-03-13 10:40:50 +01:00
771fbe156a
target/riscv: Convert RVXI csr insns to decodetree
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Acked-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de >
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de >
2019-03-13 10:34:06 +01:00
0c865e856a
target/riscv: Convert RVXI fence insns to decodetree
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Acked-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de >
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de >
2019-03-13 10:34:06 +01:00
b73a987b09
target/riscv: Convert RVXI arithmetic insns to decodetree
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we cannot remove the call to gen_arith() in decode_RV32_64G() since it
is used to translate multiply instructions.
Acked-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de >
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de >
2019-03-13 10:34:06 +01:00
7e45a682ed
target/riscv: Convert RV64I load/store insns to decodetree
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this splits the 64-bit only instructions into its own decode file such
that we generate the decoder for these instructions only for the RISC-V
64 bit target.
Acked-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de >
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de >
2019-03-13 10:34:06 +01:00
c1000d4e1b
target/riscv: Convert RV32I load/store insns to decodetree
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Acked-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de >
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de >
2019-03-13 10:34:06 +01:00
3cca75a6fe
target/riscv: Convert RVXI branch insns to decodetree
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Acked-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Palmer Dabbelt <palmer@sifive.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de >
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de >
2019-03-13 10:34:06 +01:00
2a53cff418
target/riscv: Activate decodetree and implemnt LUI & AUIPC
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for now only LUI & AUIPC are decoded and translated. If decodetree fails, we
fall back to the old decoder.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Acked-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de >
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de >
2019-03-13 10:34:06 +01:00
