864806156a
target/arm: Move CPU state dumping routines to cpu.c
...
Suggested-by: Samuel Ortiz <sameo@linux.intel.com >
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com >
Message-id: 20190701132516.26392-11-philmd@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2019-07-01 17:29:00 +01:00
d6a092d479
target/arm: Move vfp_expand_imm() to translate.[ch]
...
We want to use vfp_expand_imm() in the AArch32 VFP decode;
move it from the a64-only header/source file to the
AArch32 one (which is always compiled even for AArch64).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com >
Message-id: 20190613163917.28589-2-peter.maydell@linaro.org
2019-06-17 15:14:19 +01:00
3a7a2b4e5c
target/arm: Use tcg_gen_gvec_bitsel
...
This replaces 3 target-specific implementations for BIT, BIF, and BSL.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Message-id: 20190518191934.21887-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2019-06-13 15:14:03 +01:00
2fc0cc0e1e
target/arm: Use env_cpu, env_archcpu
...
Cleanup in the boilerplate that each target must define.
Replace arm_env_get_cpu with env_archcpu. The combination
CPU(arm_env_get_cpu) should have used ENV_GET_CPU to begin;
use env_cpu now.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2019-06-10 07:03:34 -07:00
a40ec84ee2
tcg: Create struct CPUTLB
...
Move all softmmu tlb data into this structure. Arrange the
members so that we are able to place mask+table together and
at a smaller absolute offset from ENV.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Acked-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2019-06-10 07:03:34 -07:00
f1672e6f2b
semihosting: move semihosting configuration into its own directory
...
In preparation for having some more common semihosting code let's
excise the current config magic from vl.c into its own file. We shall
later add more conditionals to the build configurations so we can
avoid building this if we don't need it.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org >
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com >
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
2019-05-28 10:28:50 +01:00
87eb65a3c4
target/arm: Simplify BFXIL expansion
...
The mask implied by the extract is redundant with the one
implied by the deposit. Also, fix spelling of BFXIL.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20190514011129.11330-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2019-05-23 14:47:43 +01:00
80ac954c36
target/arm: Use extract2 for EXTR
...
This is, after all, how we implement extract2 in tcg/aarch64.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20190514011129.11330-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2019-05-23 14:47:43 +01:00
4e027a7106
target/arm: Use tcg_gen_abs_i64 and tcg_gen_gvec_abs
...
Reviewed-by: Alex Bennée <alex.bennee@linaro.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2019-05-13 22:52:08 +00:00
90c84c5600
qom/cpu: Simplify how CPUClass:cpu_dump_state() prints
...
CPUClass method dump_statistics() takes an fprintf()-like callback and
a FILE * to pass to it. Most callers pass fprintf() and stderr.
log_cpu_state() passes fprintf() and qemu_log_file.
hmp_info_registers() passes monitor_fprintf() and the current monitor
cast to FILE *. monitor_fprintf() casts it right back, and is
otherwise identical to monitor_printf().
The callback gets passed around a lot, which is tiresome. The
type-punning around monitor_fprintf() is ugly.
Drop the callback, and call qemu_fprintf() instead. Also gets rid of
the type-punning, since qemu_fprintf() takes NULL instead of the
current monitor cast to FILE *.
Signed-off-by: Markus Armbruster <armbru@redhat.com >
Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com >
Message-Id: <20190417191805.28198-15-armbru@redhat.com >
2019-04-18 22:18:59 +02:00
a036f5302c
target/arm: Fix non-parallel expansion of CASP
...
The second word has been loaded from the unincremented
address since the first commit.
Fixes: 44ac14b06falex.bennee@linaro.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alex Bennée <alex.bennee@linaro.org >
Tested-by: Alex Bennée <alex.bennee@linaro.org >
Message-id: 20190322234302.12770-1-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2019-03-25 14:16:46 +00:00
6bea25631a
target/arm: Implement ARMv8.5-FRINT
...
Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20190301200501.16533-11-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2019-03-05 15:55:08 +00:00
0e4db23d1f
target/arm: Restructure handle_fp_1src_{single, double}
...
This will allow sharing code that adjusts rmode beyond
the existing users.
Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20190301200501.16533-10-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2019-03-05 15:55:08 +00:00
5ef84f1114
target/arm: Implement ARMv8.5-CondM
...
Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20190301200501.16533-9-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2019-03-05 15:55:08 +00:00
b89d9c988a
target/arm: Implement ARMv8.4-CondM
...
Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20190301200501.16533-8-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
[PMM: fixed up block comment style]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2019-03-05 15:55:08 +00:00
2fba34f70d
target/arm: Rearrange disas_data_proc_reg
...
This decoding more closely matches the ARMv8.4 Table C4-6,
Encoding table for Data Processing - Register Group.
In particular, op2 == 0 is now more than just Add/sub (with carry).
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20190301200501.16533-7-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2019-03-05 15:55:08 +00:00
22ac3c4964
target/arm: Add set/clear_pstate_bits, share gen_ss_advance
...
We do not need an out-of-line helper for manipulating bits in pstate.
While changing things, share the implementation of gen_ss_advance.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20190301200501.16533-6-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2019-03-05 15:55:08 +00:00
ff730e9666
target/arm: Split helper_msr_i_pstate into 3
...
The EL0+UMA check is unique to DAIF. While SPSel had avoided the
check by nature of already checking EL >= 1, the other post v8.0
extensions to MSR (imm) allow EL0 and do not require UMA. Avoid
the unconditional write to pc and use raise_exception_ra to unwind.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20190301200501.16533-5-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2019-03-05 15:55:08 +00:00
9888bd1e20
target/arm: Implement ARMv8.0-SB
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20190301200501.16533-3-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2019-03-05 15:55:07 +00:00
0caa5af802
target/arm: Implement FMLAL and FMLSL for aarch64
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20190219222952.22183-3-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2019-02-28 11:03:05 +00:00
6c1f6f2733
target/arm: Implement ARMv8.3-JSConv
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20190215192302.27855-5-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
[PMM: fixed a couple of comment typos]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2019-02-21 18:17:46 +00:00
3c3ff68492
target/arm: Restructure disas_fp_int_conv
...
For opcodes 0-5, move some if conditions into the structure
of a switch statement. For opcodes 6 & 7, decode everything
at once with a second switch.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20190215192302.27855-2-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2019-02-21 18:17:45 +00:00
89e68b575e
target/arm: Use vector operations for saturation
...
For same-sign saturation, we have tcg vector operations. We can
compute the QC bit by comparing the saturated value against the
unsaturated value.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20190209033847.9014-12-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2019-02-15 09:56:41 +00:00
264d2a481a
target/arm: Use vector minmax expanders for aarch64
...
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20190209033847.9014-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2019-02-15 09:56:40 +00:00
2900847ff4
target/arm: Rely on optimization within tcg_gen_gvec_or
...
Since we're now handling a == b generically, we no longer need
to do it by hand within target/arm/.
Reviewed-by: David Gibson <david@gibson.dropbear.id.au >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20190209033847.9014-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2019-02-15 09:56:39 +00:00
3a471103ac
target/arm: Clean TBI for data operations in the translator
...
This will allow TBI to be used in user-only mode, as well as
avoid ping-ponging the softmmu TLB when TBI is in use. It
will also enable other armv8 extensions.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20190204132126.3255-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2019-02-05 16:52:40 +00:00
4a9ee99db3
target/arm: Add TBFLAG_A64_TBID, split out gen_top_byte_ignore
...
Split out gen_top_byte_ignore in preparation of handling these
data accesses; the new tbflags field is not yet honored.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20190204132126.3255-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2019-02-05 16:52:39 +00:00
001d47b6ef
target/arm: Set btype for indirect branches
...
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20190128223118.5255-9-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2019-02-05 16:52:38 +00:00
3586227035
target/arm: Reset btype for direct branches
...
This is all of the non-exception cases of DISAS_NORETURN.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Message-id: 20190128223118.5255-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2019-02-05 16:52:38 +00:00
51bf0d7aa9
target/arm: Default handling of BTYPE during translation
...
The branch target exception for guarded pages has high priority,
and only 8 instructions are valid for that case. Perform this
check before doing any other decode.
Clear BTYPE after all insns that neither set BTYPE nor exit via
exception (DISAS_NORETURN).
Not yet handled are insns that exit via DISAS_NORETURN for some
other reason, like direct branches.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20190128223118.5255-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2019-02-05 16:52:37 +00:00
08f1434a71
target/arm: Add BT and BTYPE to tb->flags
...
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20190128223118.5255-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2019-02-05 16:52:36 +00:00
f6e52eaac1
target/arm: Add PSTATE.BTYPE
...
Place this in its own field within ENV, as that will
make it easier to reset from within TCG generated code.
With the change to pstate_read/write, exception entry
and return are automatically handled.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20190128223118.5255-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2019-02-05 16:52:36 +00:00
1cf86a8618
target/arm: fix decoding of B{,L}RA{A,B}
...
A flawed test lead to the instructions always being treated as
unallocated encodings.
Fixes: https://bugs.launchpad.net/bugs/1813460
Signed-off-by: Remi Denis-Courmont <remi.denis.courmont@huawei.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2019-02-01 15:25:24 +00:00
eaefb97a8b
target/arm/translate-a64: Fix mishandling of size in FCMLA decode
...
In disas_simd_indexed(), for the case of "complex fp", each indexable
element is a complex pair, so the total size is twice that indicated
in the 'size' field in the encoding. We were trying to do this
"double the size" operation with a left shift by 1, but this is
incorrect because the 'size' field is a MO_8/MO_16/MO_32/MO_64
value, and doubling the size should be done by a simple increment.
This meant we were mishandling FCMLA (by element) of values where
the real and imaginary parts are 32-bit floats, and would incorrectly
UNDEF this encoding. (No other insns take this code path, and for
16-bit floats it happens that 1 << 1 and 1 + 1 are both the same).
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com >
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com >
Message-id: 20190129140411.682-3-peter.maydell@linaro.org
2019-02-01 14:55:45 +00:00
4dfabb6d56
target/arm/translate-a64: Fix FCMLA decoding error
...
The FCMLA (by element) instruction exists in the
"vector x indexed element" encoding group, but not in
the "scalar x indexed element" group. Correctly UNDEF
the unallocated encodings.
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com >
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com >
Message-id: 20190129140411.682-2-peter.maydell@linaro.org
2019-02-01 14:55:45 +00:00
4977986ca3
target/arm/translate-a64: Don't underdecode SDOT and UDOT
...
In the AdvSIMD scalar x indexed element and vector x indexed element
encoding group, the SDOT and UDOT instructions are vector only,
and their opcode is unallocated in the scalar group. Correctly
UNDEF this unallocated encoding.
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com >
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com >
Message-id: 20190125182626.9221-8-peter.maydell@linaro.org
2019-02-01 14:55:45 +00:00
c1e20801f5
target/arm/translate-a64: Don't underdecode FP insns
...
In the encoding groups
* floating-point data-processing (1 source)
* floating-point data-processing (2 source)
* floating-point data-processing (3 source)
* floating-point immediate
* floating-point compare
* floating-ponit conditional compare
* floating-point conditional select
bit 31 is M and bit 29 is S (and bit 30 is 0, already checked at
this point in the decode). None of these groups allocate any
encoding for M=1 or S=1. We checked this in disas_fp_compare(),
disas_fp_ccomp() and disas_fp_csel(), but missed it in disas_fp_1src(),
disas_fp_2src(), disas_fp_3src() and disas_fp_imm().
We also missed that in the fp immediate encoding the imm5 field
must be all zeroes.
Correctly UNDEF the unallocated encodings here.
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com >
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com >
Message-id: 20190125182626.9221-7-peter.maydell@linaro.org
2019-02-01 14:55:45 +00:00
4f61106614
target/arm/translate-a64: Don't underdecode add/sub extended register
...
In the "add/subtract (extended register)" encoding group, the "opt"
field in bits [23:22] must be zero. Correctly UNDEF the unallocated
encodings where this field is not zero.
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com >
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com >
Message-id: 20190125182626.9221-6-peter.maydell@linaro.org
2019-02-01 14:55:44 +00:00
9c72b68ad7
target/arm/translate-a64: Don't underdecode SIMD ld/st single
...
In the AdvSIMD load/store single structure encodings, the
non-post-indexed case should have zeroes in [20:16] (which is the
Rm field for the post-indexed case). Bit 31 must also be zero
(a check we got right in ldst_multiple but not here). Correctly
UNDEF these unallocated encodings.
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com >
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com >
Message-id: 20190125182626.9221-5-peter.maydell@linaro.org
2019-02-01 14:55:44 +00:00
e1f220811d
target/arm/translate-a64: Don't underdecode SIMD ld/st multiple
...
In the AdvSIMD load/store multiple structures encodings,
the non-post-indexed case should have zeroes in [20:16]
(which is the Rm field for the post-indexed case).
Correctly UNDEF the currently unallocated encodings which
have non-zeroes in those bits.
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com >
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com >
Message-id: 20190125182626.9221-4-peter.maydell@linaro.org
2019-02-01 14:55:44 +00:00
a80c425654
target/arm/translate-a64: Don't underdecode PRFM
...
The PRFM prefetch insn in the load/store with imm9 encodings
requires idx field 0b00; we were underdecoding this by
only checking !is_unpriv (which is equivalent to idx != 2).
Correctly UNDEF the unallocated encodings where idx == 0b01
and 0b11 as well as 0b10.
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com >
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com >
Message-id: 20190125182626.9221-3-peter.maydell@linaro.org
2019-02-01 14:55:44 +00:00
08d5e3bde6
target/arm/translate-a64: Don't underdecode system instructions
...
The "system instructions" and "system register move" subcategories
of "branches, exception generating and system instructions" for A64
only apply if bits [23:22] are zero; other values are currently
unallocated. Correctly UNDEF these unallocated encodings.
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com >
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com >
Message-id: 20190125182626.9221-2-peter.maydell@linaro.org
2019-02-01 14:55:44 +00:00
8733d762d5
target/arm: Tidy TBI handling in gen_a64_set_pc
...
We can perform this with fewer operations.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20190108223129.5570-32-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2019-01-21 10:38:55 +00:00
476a4692f0
target/arm: Merge TBFLAG_AA_TB{0, 1} to TBII
...
We will shortly want to talk about TBI as it relates to data.
Passing around a pair of variables is less convenient than a
single variable.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Message-id: 20190108223129.5570-20-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2019-01-21 10:38:54 +00:00
bd889f4810
target/arm: Decode Load/store register (pac)
...
Not that there are any stores involved, but why argue with ARM's
naming convention.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Message-id: 20190108223129.5570-15-richard.henderson@linaro.org
[fixed trivial comment nit]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2019-01-21 10:38:53 +00:00
561c0a3308
target/arm: Decode PAuth within disas_uncond_b_reg
...
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20190108223129.5570-14-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2019-01-21 10:38:53 +00:00
f7cf3bfc1b
target/arm: Rearrange decode in disas_uncond_b_reg
...
This will enable PAuth decode in a subsequent patch.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Message-id: 20190108223129.5570-13-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2019-01-21 10:38:53 +00:00
d9f482a027
target/arm: Add new_pc argument to helper_exception_return
...
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20190108223129.5570-12-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2019-01-21 10:38:53 +00:00
b6342a9f92
target/arm: Decode PAuth within disas_data_proc_2src
...
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20190108223129.5570-10-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2019-01-21 10:38:53 +00:00
95ebd99dcd
target/arm: Decode PAuth within disas_data_proc_1src
...
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20190108223129.5570-9-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2019-01-21 10:38:53 +00:00
