ff730e9666
target/arm: Split helper_msr_i_pstate into 3
...
The EL0+UMA check is unique to DAIF. While SPSel had avoided the
check by nature of already checking EL >= 1, the other post v8.0
extensions to MSR (imm) allow EL0 and do not require UMA. Avoid
the unconditional write to pc and use raise_exception_ra to unwind.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20190301200501.16533-5-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2019-03-05 15:55:08 +00:00
d9f482a027
target/arm: Add new_pc argument to helper_exception_return
...
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20190108223129.5570-12-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2019-01-21 10:38:53 +00:00
ce02fd99e6
target/arm: Move helper_exception_return to helper-a64.c
...
This function is only used by AArch64. Code movement only.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20190108223129.5570-11-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2019-01-21 10:38:53 +00:00
0d43e1a2d2
target/arm: Add PAuth helpers
...
The cryptographic internals are stubbed out for now,
but the enable and trap bits are checked.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Message-id: 20190108223129.5570-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2019-01-21 10:38:53 +00:00
7a1929256e
target/arm: Implement FCMP for fp16
...
These where missed out from the rest of the half-precision work.
Cc: qemu-stable@nongnu.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Alex Bennée <alex.bennee@linaro.org >
Tested-by: Alex Bennée <alex.bennee@linaro.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20180512003217.9105-9-richard.henderson@linaro.org
[rth: Diagnose lack of FP16 before fp_access_check]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2018-05-15 14:58:43 +01:00
44ac14b06f
target/arm: Implement CAS and CASP
...
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20180508151437.4232-10-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2018-05-10 18:10:57 +01:00
b96a54c7e5
arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16
...
Signed-off-by: Alex Bennée <alex.bennee@linaro.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20180227143852.11175-26-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2018-03-01 11:13:59 +00:00
9869502838
arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16
...
We go with the localised helper.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20180227143852.11175-25-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2018-03-01 11:13:59 +00:00
2df5813041
arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16
...
This covers all the floating point convert operations.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20180227143852.11175-19-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2018-03-01 11:13:59 +00:00
6109aea2d9
arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16
...
This adds the full range of half-precision floating point to integral
instructions.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20180227143852.11175-18-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2018-03-01 11:13:59 +00:00
6089030c73
arm/translate-a64: add FP16 x2 ops for simd_indexed
...
A bunch of the vectorised bitwise operations just operate on larger
chunks at a time. We can do the same for the new half-precision
operations by introducing some TWOHALFOP helpers which work on each
half of a pair of half-precision operations at once.
Hopefully all this hoop jumping will get simpler once we have
generically vectorised helpers here.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20180227143852.11175-16-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2018-03-01 11:13:59 +00:00
026e2d6ef7
arm/translate-a64: add FP16 FR[ECP/SQRT]S to simd_three_reg_same_fp16
...
As some of the constants here will also be needed
elsewhere (specifically for the upcoming SVE support) we move them out
to softfloat.h.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20180227143852.11175-13-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2018-03-01 11:13:59 +00:00
2deb992b76
arm/translate-a64: add FP16 FMULA/X/S to simd_three_reg_same_fp16
...
Signed-off-by: Alex Bennée <alex.bennee@linaro.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20180227143852.11175-12-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2018-03-01 11:13:59 +00:00
d32adeae1a
arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to simd_three_reg_same_fp16
...
These use the generic float16_compare functionality which in turn uses
the common float_compare code from the softfloat re-factor.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20180227143852.11175-11-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2018-03-01 11:13:59 +00:00
372087348d
arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to simd_three_reg_same_fp16
...
The fprintf is only there for debugging as the skeleton is added to,
it will be removed once the skeleton is complete.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20180227143852.11175-10-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2018-03-01 11:13:59 +00:00
807cdd5042
arm/translate-a64: implement half-precision F(MIN|MAX)(V|NMV)
...
This implements the half-precision variants of the across vector
reduction operations. This involves a re-factor of the reduction code
which more closely matches the ARM ARM order (and handles 8 element
reductions).
Signed-off-by: Alex Bennée <alex.bennee@linaro.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20180227143852.11175-7-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2018-03-01 11:13:59 +00:00
2399d4e7ce
target/arm: check CF_PARALLEL instead of parallel_cpus
...
Thereby decoupling the resulting translated code from the current state
of the system.
Reviewed-by: Richard Henderson <rth@twiddle.net >
Signed-off-by: Emilio G. Cota <cota@braap.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2017-10-24 13:53:41 -07:00
bc21dbcc12
target-arm: Use clrsb helper
...
Reviewed-by: Alex Bennée <alex.bennee@linaro.org >
Signed-off-by: Richard Henderson <rth@twiddle.net >
2017-01-10 08:47:48 -08:00
7539a012f6
target-arm: Use clz opcode
...
Reviewed-by: Alex Bennée <alex.bennee@linaro.org >
Signed-off-by: Richard Henderson <rth@twiddle.net >
2017-01-10 08:06:11 -08:00
fcf5ef2ab5
Move target-* CPU file into a target/ folder
...
We've currently got 18 architectures in QEMU, and thus 18 target-xxx
folders in the root folder of the QEMU source tree. More architectures
(e.g. RISC-V, AVR) are likely to be included soon, too, so the main
folder of the QEMU sources slowly gets quite overcrowded with the
target-xxx folders.
To disburden the main folder a little bit, let's move the target-xxx
folders into a dedicated target/ folder, so that target-xxx/ simply
becomes target/xxx/ instead.
Acked-by: Laurent Vivier <laurent@vivier.eu > [m68k part]
Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de > [tricore part]
Acked-by: Michael Walle <michael@walle.cc > [lm32 part]
Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com > [s390x part]
Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com > [s390x part]
Acked-by: Eduardo Habkost <ehabkost@redhat.com > [i386 part]
Acked-by: Artyom Tarasenko <atar4qemu@gmail.com > [sparc part]
Acked-by: Richard Henderson <rth@twiddle.net > [alpha part]
Acked-by: Max Filippov <jcmvbkbc@gmail.com > [xtensa part]
Reviewed-by: David Gibson <david@gibson.dropbear.id.au > [ppc part]
Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com > [crisµblaze part]
Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn > [unicore32 part]
Signed-off-by: Thomas Huth <thuth@redhat.com >
2016-12-20 21:52:12 +01:00
