6533a1fcc2
hw/cpu/{a15mpcore, a9mpcore}: Handle missing has_el3 CPU props gracefully
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Handle missing CPU support for EL3 gracefully.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com >
Message-id: 1442135278-25281-2-git-send-email-edgar.iglesias@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-09-14 14:39:49 +01:00
4182bbb19d
hw/cpu/{a15mpcore, a9mpcore}: enable TrustZone in GIC if it is enabled in CPUs
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If the A9 and A15 CPUs which we're creating the peripherals for have
TrustZone (EL3) enabled, then also enable it in the GIC we create.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com >
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com >
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com >
Message-id: 1441383782-24378-5-git-send-email-peter.maydell@linaro.org
2015-09-08 17:38:43 +01:00
5dfaa75b4d
hw/cpu/a15mpcore: Wire up hyp and secure physical timer interrupts
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Since we now support both the hypervisor and the secure physical timer, wire
their interrupt lines up in the a15mpcore wrapper object.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
Message-id: 1437047249-2357-5-git-send-email-peter.maydell@linaro.org
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com >
2015-08-13 11:26:22 +01:00
e6fbcbc4e5
Introduce gic_class_name() instead of repeating condition
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This small inline returns correct GIC class name depending on whether we
use KVM acceleration or not. Avoids duplicating the condition everywhere.
Signed-off-by: Pavel Fedin <p.fedin@samsung.com >
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Message-id: 4f26901be9b844b563673ce3ad08eeedbb7a7132.1438758065.git.p.fedin@samsung.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-08-13 11:26:21 +01:00
43482f72db
a15mpcore: Prepare for QOM embedding
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Andreas Färber <andreas.faerber@web.de >
2013-11-05 17:47:30 +01:00
7c76a48db4
a15mpcore: Convert to QOM realize
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Turn SysBusDevice initfn into a QOM realizefn.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Andreas Färber <andreas.faerber@web.de >
2013-11-05 17:47:30 +01:00
524a2d8e26
a15mpcore: Embed GICState
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This covers both emulated and KVM GIC.
Prepares for QOM realize.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Andreas Färber <andreas.faerber@web.de >
2013-11-05 17:47:30 +01:00
b9ed148d24
a15mpcore: Split off instance_init
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Prepares for QOM realize.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Andreas Färber <andreas.faerber@web.de >
2013-11-05 17:47:30 +01:00
27013bf20d
a15mpcore: Use qemu_get_cpu() for generic timers
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This simplifies the loop and aids with refactoring of CPU list.
Requested-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Andreas Färber <afaerber@suse.de >
2013-09-03 11:30:04 +02:00
6033e840c7
hw/cpu/a15mpcore: Wire generic timer outputs to GIC inputs
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Now our A15 CPU implements the generic timers, we can wire them
up to the appropriate inputs on the GIC.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com >
Message-id: 1376065080-26661-5-git-send-email-peter.maydell@linaro.org
2013-08-20 14:54:32 +01:00
97da11d857
cpu/a15mpcore: QOM cast cleanup
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Introduce type constant and cast macro and rename A15MPPrivState::busdev
field to parent_obj to enforce its use.
Prepares for QOM realize.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Andreas Färber <andreas.faerber@web.de >
2013-07-29 20:42:00 +02:00
528622421e
hw/cpu/a15mpcore: Correct default value for num-irq
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The a15mpcore device claims that its default value for num-irq
is the number of interrupts used by the A15MP in the vexpress-a15
board. However that chip has 128 external interrupts, not 64.
Since there is only one A15 based model in QEMU currently, we
can fix this by simply changing the default value.
This error was causing recent (3.10) Linux kernels to print
warnings/backtraces when the number of interrupts reported
by the GIC was smaller than an interrupt number they wanted
to use.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
Message-id: 1373032481-15280-1-git-send-email-peter.maydell@linaro.org
2013-07-15 16:17:02 +01:00
300b1fc68c
hw/c*: pass owner to memory_region_init* functions
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com >
2013-07-04 17:42:47 +02:00
2c9b15cab1
memory: add owner argument to initialization functions
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com >
2013-07-04 17:42:44 +02:00
0434e30afb
hw: move ARM CPU cores to hw/cpu/, configure with default-configs/
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com >
2013-04-08 18:13:16 +02:00
