cffa995490
disas/riscv: Fix the typo of inverted order of pmpaddr13 and pmpaddr14
...
Fix the inverted order of pmpaddr13 and pmpaddr14 in csr_name().
Signed-off-by: Alvin Chang <alvinga@andestech.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-ID: <20230907084500.328-1-alvinga@andestech.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-10-12 11:53:47 +10:00
36df75a0a9
riscv/disas: Fix disas output of upper immediates
...
The GNU assembler produces the following output for instructions
with upper immediates:
00002597 auipc a1,0x2
000024b7 lui s1,0x2
6409 lui s0,0x2 # c.lui
The immediate operands of upper immediates are not shifted.
However, the QEMU disassembler prints them shifted:
00002597 auipc a1,8192
000024b7 lui s1,8192
6409 lui s0,8192 # c.lui
The current implementation extracts the immediate bits and shifts the by 12,
so the internal representation of the immediate is the actual immediate.
However, the immediates are later printed using rv_fmt_rd_imm or
rv_fmt_rd_offset, which don't undo the shift.
Let's fix this by using specific output formats for instructions
with upper immediates, that take care of the shift.
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu >
Acked-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20230711075051.1531007-1-christoph.muellner@vrull.eu >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-07-19 14:30:04 +10:00
a47842d166
riscv: Add support for the Zfa extension
...
This patch introduces the RISC-V Zfa extension, which introduces
additional floating-point instructions:
* fli (load-immediate) with pre-defined immediates
* fminm/fmaxm (like fmin/fmax but with different NaN behaviour)
* fround/froundmx (round to integer)
* fcvtmod.w.d (Modular Convert-to-Integer)
* fmv* to access high bits of float register bigger than XLEN
* Quiet comparison instructions (fleq/fltq)
Zfa defines its instructions in combination with the following extensions:
* single-precision floating-point (F)
* double-precision floating-point (D)
* quad-precision floating-point (Q)
* half-precision floating-point (Zfh)
Since QEMU does not support the RISC-V quad-precision floating-point
ISA extension (Q), this patch does not include the instructions that
depend on this extension. All other instructions are included in this
patch.
The Zfa specification can be found here:
https://github.com/riscv/riscv-isa-manual/blob/master/src/zfa.tex
The Zfa specifciation is frozen and is in public review since May 3, 2023:
https://groups.google.com/a/groups.riscv.org/g/isa-dev/c/SED4ntBkabg
The patch also includes a TCG test for the fcvtmod.w.d instruction.
The test cases test for correct results and flag behaviour.
Note, that the Zfa specification requires fcvtmod's flag behaviour
to be identical to a fcvt with the same operands (which is also
tested).
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu >
Message-Id: <20230710071243.282464-1-christoph.muellner@vrull.eu >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-07-10 22:29:20 +10:00
32b2d75bf7
target/riscv: Add disas support for BF16 extensions
...
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn >
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn >
Acked-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20230703071759.86775-2-liweiwei@iscas.ac.cn >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-07-10 22:29:15 +10:00
318df7238b
disas/riscv: Add support for XThead* instructions
...
Support for emulating XThead* instruction has been added recently.
This patch adds support for these instructions to the RISC-V disassembler.
Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com >
Acked-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu >
Message-Id: <20230612111034.3955227-9-christoph.muellner@vrull.eu >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-07-10 22:29:14 +10:00
f6f72338d8
disas/riscv: Add support for XVentanaCondOps
...
This patch adds XVentanaCondOps support to the RISC-V disassembler.
Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com >
Acked-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu >
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com >
Message-Id: <20230612111034.3955227-8-christoph.muellner@vrull.eu >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-07-10 22:29:14 +10:00
c859a2424d
disas/riscv: Provide infrastructure for vendor extensions
...
A previous patch provides a pointer to the RISCVCPUConfig data.
Let's use this to add the necessary code for vendor extensions.
This patch does not change the current behaviour, but clearly
defines how vendor extension support can be added to the disassembler.
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu >
Message-Id: <20230612111034.3955227-7-christoph.muellner@vrull.eu >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-07-10 22:29:14 +10:00
fd7c64f6bd
disas/riscv: Encapsulate opcode_data into decode
...
This patch adds a reference to a struct rv_opcode_data object
into struct rv_decode. This further allows to remove all references
to the global variable opcode_data (which is renamed to rvi_opcode_data).
This patch does not introduce any functional change, but prepares
the code for more struct rv_opcode_data objects in the future.
This patch is based on previous work from Liu Zhiwei:
https://lists.nongnu.org/archive/html/qemu-devel/2022-08/msg03662.html
Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu >
Message-Id: <20230612111034.3955227-6-christoph.muellner@vrull.eu >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-07-10 22:29:14 +10:00
01b1361f84
disas/riscv: Make rv_op_illegal a shared enum value
...
The enum value 'rv_op_illegal' does not represent an
instruction, but is a catch-all value in case we have
no match in the decoder. Let's make the value a shared
one, so that other compile units can reuse it.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com >
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu >
Message-Id: <20230612111034.3955227-5-christoph.muellner@vrull.eu >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-07-10 22:29:14 +10:00
5d326db2f9
disas/riscv: Move types/constants to new header file
...
In order to enable vendor disassembler support, we need to
move types and constants into a header file so that other
compilation units can use them as well.
This patch does not introduce any functional changes.
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu >
Message-Id: <20230612111034.3955227-4-christoph.muellner@vrull.eu >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-07-10 22:29:14 +10:00
3bd87176ee
disas/riscv.c: Remove redundant parentheses
...
Remove redundant parenthese and fix multi-line comments.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn >
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn >
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com >
Acked-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20230523093539.203909-9-liweiwei@iscas.ac.cn >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-06-13 17:31:35 +10:00
98624d1373
disas/riscv.c: Fix lines with over 80 characters
...
Fix lines with over 80 characters.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn >
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn >
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com >
Acked-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20230523093539.203909-8-liweiwei@iscas.ac.cn >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-06-13 17:30:47 +10:00
8deb4756a9
disas/riscv.c: Remove unused decomp_rv32/64 value for vector instructions
...
Currently decomp_rv32 and decomp_rv64 value in opcode_data for vector
instructions are the same op index as their own. And they have no
functional decomp_data. So they have no functional difference from just
leaving them as zero.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn >
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn >
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com >
Acked-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20230523093539.203909-7-liweiwei@iscas.ac.cn >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-06-13 17:29:59 +10:00
c54dab4c85
disas/riscv.c: Support disas for Z*inx extensions
...
Support disas for Z*inx instructions only when Zfinx extension is supported.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn >
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn >
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20230523093539.203909-6-liweiwei@iscas.ac.cn >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-06-13 17:29:10 +10:00
2a2b221b65
disas/riscv.c: Support disas for Zcm* extensions
...
Support disas for Zcmt* instructions only when related extensions
are supported.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn >
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn >
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20230523093539.203909-5-liweiwei@iscas.ac.cn >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-06-13 17:28:22 +10:00
454c220100
target/riscv: Pass RISCVCPUConfig as target_info to disassemble_info
...
Pass RISCVCPUConfig as disassemble_info.target_info to support disas
of conflict instructions related to specific extensions.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn >
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn >
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20230523093539.203909-4-liweiwei@iscas.ac.cn >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-06-13 17:27:33 +10:00
d397be9a22
disas/riscv: Decode czero.{eqz,nez}
...
Acked-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2023-05-25 13:57:52 +00:00
2c71d02e17
disas/riscv.c: add disasm support for Zc*
...
Zcmp/Zcmt instructions will override disasm for c.fld*/c.fsd*
instructions currently.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn >
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn >
Acked-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20230307081403.61950-10-liweiwei@iscas.ac.cn >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-05-05 10:49:50 +10:00
0d581506de
Fix incorrect register name in disassembler for fmv,fabs,fneg instructions
...
Fix incorrect register name in RISC-V disassembler for fmv,fabs,fneg instructions
Signed-off-by: Mikhail Tyutin <m.tyutin@yadro.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <3454991f-7f64-24c3-9a36-f5fa2cc389e1@yadro.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-03-14 16:36:43 +10:00
13e269f64a
disas/riscv: Fix slli_uw decoding
...
The decoding of the slli_uw currently contains decoding
error: shamt part of opcode has six bits, not five.
Fixes 3de1fb71("target/riscv: update disas.c for xnor/orn/andn and slli.uw")
Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com >
Reviewed-by: Philipp Tomsich <philipp.tomsich@vrull.eu >
Acked-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20230227090228.17117-1-ivan.klokov@syntacore.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-03-14 16:36:30 +10:00
270629024d
disas/riscv Fix ctzw disassemble
...
Due to typo in opcode list, ctzw is disassembled as clzw instruction.
Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com >
Fixes: 02c1b569a1liweiwei@iscas.ac.cn >
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com >
Message-ID: <20230217151459.54649-1-ivan.klokov@syntacore.com >
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com >
2023-03-05 12:43:38 -08:00
3de1fb712a
target/riscv: update disas.c for xnor/orn/andn and slli.uw
...
The decoding of the following instructions from Zb[abcs] currently
contains decoding/printing errors:
* xnor,orn,andn: the rs2 operand is not being printed
* slli.uw: decodes and prints the immediate shift-amount as a
register (e.g. 'shift-by-2' becomes 'sp') instead of
interpreting this as an immediate
This commit updates the instruction descriptions to use the
appropriate decoding/printing formats.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20230120151551.1022761-1-philipp.tomsich@vrull.eu >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-02-07 08:19:22 +10:00
07f4964d17
disas/riscv.c: rvv: Add disas support for vector instructions
...
Tested with https://github.com/ksco/rvv-decoder-tests
Expected checkpatch errors for consistency and brevity reasons:
ERROR: line over 90 characters
ERROR: trailing statements should be on next line
ERROR: braces {} are necessary for all arms of this statement
Signed-off-by: Yang Liu <liuyang22@iscas.ac.cn >
Acked-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20220928051842.16207-1-liuyang22@iscas.ac.cn >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-10-14 14:29:50 +10:00
513eb437ae
target/riscv: Remove sideleg and sedeleg
...
sideleg and sedeleg csrs are not part of riscv isa spec
anymore, these csrs were part of N extension which
is removed from the riscv isa specification.
These commits removed all traces of these csrs from
riscv spec (https://github.com/riscv/riscv-isa-manual ) -
commit f8d27f805b65 ("Remove or downgrade more references to N extension (#674 )")
commit b6cade07034d ("Remove N extension chapter for now")
Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com >
Reviewed-by: Andrew Jones <ajones@ventanamicro.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20220824145255.400040-1-rpathak@ventanamicro.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-09-27 07:04:38 +10:00
3363277525
target/riscv: fix shifts shamt value for rv128c
...
For rv128c shifts, a shamt of 0 is a shamt of 64, while for rv32c/rv64c
it stays 0 and is a hint instruction that does not change processor state.
For rv128c right shifts, the 6-bit shamt is in addition sign extended to
7 bits.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr >
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20220710110451.245567-1-frederic.petrot@univ-grenoble-alpes.fr >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-09-07 09:18:32 +02:00
5748c886b1
disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions
...
Co-authored-by: Ruibo Lu <luruibo2000@163.com >
Co-authored-by: Zewen Ye <lustrew@foxmail.com >
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn >
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20220423023510.30794-14-liweiwei@iscas.ac.cn >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-04-29 10:47:45 +10:00
332dab6878
target/riscv: setup everything for rv64 to support rv128 execution
...
This patch adds the support of the '-cpu rv128' option to
qemu-system-riscv64 so that we can indicate that we want to run rv128
executables.
Still, there is no support for 128-bit insns at that stage so qemu fails
miserably (as expected) if launched with this option.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr >
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20220106210108.138226-8-frederic.petrot@univ-grenoble-alpes.fr
[ Changed by AF
- Rename CPU to "x-rv128"
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-01-08 15:46:10 +10:00
02c1b569a1
disas/riscv: Add Zb[abcs] instructions
...
With the addition of Zb[abcs], we also need to add disassembler
support for these new instructions.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu >
Acked-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20210911140016.834071-17-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-10-07 08:41:33 +10:00
2e3df911c5
disas/riscv: Fix rdinstreth constraint
...
The constraint for `rdinstreth` was comparing the csr number to 0xc80,
which is `cycleh` instead. Fix this.
Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com >
Signed-off-by: Michael Clark <mjc@sifive.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Palmer Dabbelt <palmer@sifive.com >
Signed-off-by: Palmer Dabbelt <palmer@sifive.com >
2019-06-27 02:47:04 -07:00
f88222dae5
disas/riscv: Disassemble reserved compressed encodings as illegal
...
Due to the design of the disassembler, the immediate is not
known during decoding of the opcode; so to handle compressed
encodings with reserved immediate values (non-zero), we need
to add an additional check during decompression to match
reserved encodings with zero immediates and translate them
into the illegal instruction.
The following compressed opcodes have reserved encodings with
zero immediates: c.addi4spn, c.addi, c.lui, c.addi16sp, c.srli,
c.srai, c.andi and c.slli
Signed-off-by: Michael Clark <mjc@sifive.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
[Palmer: Broke long lines]
Reviewed-by: Palmer Dabbelt <palmer@sifive.com >
Signed-off-by: Palmer Dabbelt <palmer@sifive.com >
2019-06-27 02:44:35 -07:00
3979fca4b6
disas: Rename include/disas/bfd.h back to include/disas/dis-asm.h
...
Commit dc99065b5f43d4145a9876cad71136pbonzini@redhat.com >
Signed-off-by: Markus Armbruster <armbru@redhat.com >
Message-Id: <20190417191805.28198-17-armbru@redhat.com >
Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com >
2019-04-18 22:18:59 +02:00
c124c15242
RISC-V: Remove unnecessary disassembler constraints
...
Remove machine generated constraints that are not
referenced by the pseudo-instruction constraints.
Cc: Palmer Dabbelt <palmer@sifive.com >
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu >
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de >
Cc: Alistair Francis <Alistair.Francis@wdc.com >
Signed-off-by: Michael Clark <mjc@sifive.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Palmer Dabbelt <palmer@sifive.com >
2019-03-19 05:14:39 -07:00
1dc34be1c9
RISC-V: Fix missing break statement in disassembler
...
This fixes an issue when disassembling rv128 c.sqsp,
where the code erroneously fell through to c.swsp.
Cc: Palmer Dabbelt <palmer@sifive.com >
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu >
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de >
Cc: Alistair Francis <Alistair.Francis@wdc.com >
Cc: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Michael Clark <mjc@sifive.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
2018-05-06 10:39:38 +12:00
6296a799b1
RISC-V: Include instruction hex in disassembly
...
This was added to help debug issues using -d in_asm. It is
useful to see the instruction bytes, as one can detect if
one is trying to execute ASCII or device-tree magic.
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu >
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de >
Signed-off-by: Michael Clark <mjc@sifive.com >
Signed-off-by: Palmer Dabbelt <palmer@sifive.com >
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
2018-05-06 10:39:38 +12:00
33b4f859f1
RISC-V: Fix incorrect disassembly for addiw
...
This fixes a bug in the disassembler constraints used
to lift instructions into pseudo-instructions, whereby
addiw instructions are always lifted to sext.w instead
of just lifting addiw with a zero immediate.
An associated fix has been made to the metadata used to
machine generate the disseasembler:
https://github.com/michaeljclark/riscv-meta/
commit/4a6b2f3898430768acfe201405224d2ea31e1477
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu >
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de >
Cc: Palmer Dabbelt <palmer@sifive.com >
Cc: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Michael Clark <mjc@sifive.com >
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
2018-03-28 11:12:02 -07:00
ea10325917
RISC-V Disassembler
...
The RISC-V disassembler has no dependencies outside of the 'disas'
directory so it can be applied independently. The majority of the
disassembler is machine-generated from instruction set metadata:
- https://github.com/michaeljclark/riscv-meta
Expected checkpatch errors for consistency and brevity reasons:
ERROR: line over 90 characters
ERROR: trailing statements should be on next line
ERROR: space prohibited between function name and open parenthesis '('
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: Michael Clark <mjc@sifive.com >
2018-03-07 08:30:28 +13:00
