ab1103def4
TCG: Use gen_opc_instr_start from context instead of global variable.
...
Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com >
Signed-off-by: Blue Swirl <blauwirbel@gmail.com >
2012-12-08 14:24:43 +00:00
c9c99c22d5
TCG: Use gen_opc_icount from context instead of global variable.
...
Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com >
Signed-off-by: Blue Swirl <blauwirbel@gmail.com >
2012-12-08 14:24:42 +00:00
25983cad31
TCG: Use gen_opc_pc from context instead of global variable.
...
Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com >
Signed-off-by: Blue Swirl <blauwirbel@gmail.com >
2012-12-08 14:24:42 +00:00
44e04d3b94
target-openrisc: remove conflicting definitions from cpu.h
...
On an ARM host, the registers definitions from cpu.h clash
with /usr/include/sys/ucontext.h. As there are unused, just remove
them.
Cc: Jia Liu <proljc@gmail.com >
Cc: qemu-stable@nongnu.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net >
2012-11-24 13:19:54 +01:00
92414b31e7
TCG: Use gen_opc_buf from context instead of global variable.
...
Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com >
Reviewed-by: Richard Henderson <rth@twiddle.net >
Signed-off-by: Blue Swirl <blauwirbel@gmail.com >
2012-11-17 13:53:36 +00:00
efd7f48600
TCG: Use gen_opc_ptr from context instead of global variable.
...
Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com >
Reviewed-by: Richard Henderson <rth@twiddle.net >
Signed-off-by: Blue Swirl <blauwirbel@gmail.com >
2012-11-17 13:53:27 +00:00
f4359b9ffe
disas: avoid using cpu_single_env
...
Pass around CPUArchState instead of using global cpu_single_env.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com >
Acked-by: Richard Henderson <rth@twiddle.net >
Acked-by: Aurelien Jarno <aurelien@aurel32.net >
Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn >
2012-11-10 13:49:20 +00:00
3993c6bddf
cpus: Pass CPUState to [qemu_]cpu_has_work()
...
For target-mips also change the return type to bool.
Make include paths for cpu-qom.h consistent for alpha and unicore32.
Signed-off-by: Andreas Färber <afaerber@suse.de >
[AF: Updated new target-openrisc function accordingly]
Acked-by: Richard Henderson <rth@twiddle.net > (for alpha)
2012-10-31 04:11:37 +01:00
a8170e5e97
Rename target_phys_addr_t to hwaddr
...
target_phys_addr_t is unwieldly, violates the C standard (_t suffixes are
reserved) and its purpose doesn't match the name (most target_phys_addr_t
addresses are not target specific). Replace it with a finger-friendly,
standards conformant hwaddr.
Outstanding patchsets can be fixed up with the command
git rebase -i --exec 'find -name "*.[ch]"
| xargs s/target_phys_addr_t/hwaddr/g' origin
Signed-off-by: Avi Kivity <avi@redhat.com >
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com >
2012-10-23 08:58:25 -05:00
fdefe51c28
Emit debug_insn for CPU_LOG_TB_OP_OPT as well.
...
For all targets that currently call tcg_gen_debug_insn_start,
add CPU_LOG_TB_OP_OPT to the condition that gates it.
This is useful for comparing optimization dumps, when the
pre-optimization dump is merely noise.
Signed-off-by: Richard Henderson <rth@twiddle.net >
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net >
2012-09-27 21:38:50 +02:00
d962783e98
target-or32: Add linux user support
...
Add QEMU OpenRISC linux user support.
Signed-off-by: Jia Liu <proljc@gmail.com >
Signed-off-by: Blue Swirl <blauwirbel@gmail.com >
2012-07-27 21:13:05 +00:00
4dd044c6ba
target-or32: Add system instructions
...
Add OpenRISC system instructions.
Signed-off-by: Jia Liu <proljc@gmail.com >
Signed-off-by: Blue Swirl <blauwirbel@gmail.com >
2012-07-27 21:13:03 +00:00
99f575edcc
target-or32: Add timer support
...
Add OpenRISC timer support.
Signed-off-by: Jia Liu <proljc@gmail.com >
Signed-off-by: Blue Swirl <blauwirbel@gmail.com >
2012-07-27 21:13:02 +00:00
dd29c7fb01
target-or32: Add PIC support
...
Add OpenRISC Programmable Interrupt Controller support.
Signed-off-by: Jia Liu <proljc@gmail.com >
Signed-off-by: Blue Swirl <blauwirbel@gmail.com >
2012-07-27 21:13:01 +00:00
bbe418f25d
target-or32: Add instruction translation
...
Add OpenRISC instruction tanslation routines.
Signed-off-by: Jia Liu <proljc@gmail.com >
Signed-off-by: Blue Swirl <blauwirbel@gmail.com >
2012-07-27 21:13:00 +00:00
5b5695073b
target-or32: Add float instruction helpers
...
Add OpenRISC float instruction helpers.
Signed-off-by: Jia Liu <proljc@gmail.com >
Signed-off-by: Blue Swirl <blauwirbel@gmail.com >
2012-07-27 21:13:00 +00:00
e54a5aff13
target-or32: Add int instruction helpers
...
Add OpenRISC int instruction helpers.
Signed-off-by: Jia Liu <proljc@gmail.com >
Signed-off-by: Blue Swirl <blauwirbel@gmail.com >
2012-07-27 21:12:59 +00:00
1d7d403469
target-or32: Add exception support
...
Add OpenRISC exception support.
Signed-off-by: Jia Liu <proljc@gmail.com >
Signed-off-by: Blue Swirl <blauwirbel@gmail.com >
2012-07-27 21:12:58 +00:00
b6a71ef7e0
target-or32: Add interrupt support
...
Add OpenRISC interrupt support.
Signed-off-by: Jia Liu <proljc@gmail.com >
Signed-off-by: Blue Swirl <blauwirbel@gmail.com >
2012-07-27 21:12:57 +00:00
726fe04572
target-or32: Add MMU support
...
Add OpenRISC MMU support.
Signed-off-by: Jia Liu <proljc@gmail.com >
Signed-off-by: Blue Swirl <blauwirbel@gmail.com >
2012-07-27 21:12:56 +00:00
e67db06e9f
target-or32: Add target stubs and QOM cpu
...
Add OpenRISC target stubs, QOM cpu and basic machine.
Signed-off-by: Jia Liu <proljc@gmail.com >
Signed-off-by: Blue Swirl <blauwirbel@gmail.com >
2012-07-27 21:12:55 +00:00
