5 Commits

Author	SHA1	Message	Date
Alistair Francis	96338fefc1	hw/intc/ibex_plic: Clear the claim register when read ... After claiming the interrupt by reading the claim register we want to clear the register to make sure the interrupt doesn't appear at the next read. This matches the documentation for the claim register as when an interrupt is claimed by a target the relevant bit of IP is cleared (which we already do): https://docs.opentitan.org/hw/ip/rv_plic/doc/index.html This also matches the current hardware. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 68d4575deef2559b7a747f3bda193fcf43af4558.1604629928.git.alistair.francis@wdc.com	2020-11-09 15:09:53 -08:00
Alistair Francis	01c41d15de	hw/intc: ibex_plic: Honour source priorities ... This patch follows what commit aa4d30f661 "riscv: plic: Honour source priorities" does and ensures that the highest priority interrupt will be serviced first. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Cc: Jessica Clarke <jrtc27@jrtc27.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <a697ca8a31eff8eb18a88e09a28206063cf85d48.1595655188.git.alistair.francis@wdc.com>	2020-08-21 22:37:55 -07:00
Alistair Francis	224914069d	hw/intc: ibex_plic: Don't allow repeat interrupts on claimed lines ... Once an interrupt has been claimed, but before it has been compelted we shouldn't receive any more pending interrupts. This patche keeps track of this to ensure that we don't see any more interrupts until it is completed. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <394c3f070615ff2b4fab61a1cf9cb48c122913b7.1595655188.git.alistair.francis@wdc.com>	2020-08-21 22:37:55 -07:00
Alistair Francis	c43388bbfd	hw/intc: ibex_plic: Update the pending irqs ... After a claim or a priority change we need to update the pending interrupts. This is based on the same patch for the SiFive PLIC: 5576582280 "riscv: plic: Add a couple of mising sifive_plic_update calls" Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Cc: Jessica Clarke <jrtc27@jrtc27.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <0693aa700a4c67c49b3f1c973a82b257fdb7198d.1595655188.git.alistair.francis@wdc.com>	2020-08-21 22:37:55 -07:00
Alistair Francis	879f60f01c	hw/intc: Initial commit of lowRISC Ibex PLIC ... The Ibex core contains a PLIC that although similar to the RISC-V spec is not RISC-V spec compliant. This patch implements a Ibex PLIC in a somewhat generic way. As the current RISC-V PLIC needs tidying up, my hope is that as the Ibex PLIC move towards spec compliance this PLIC implementation can be updated until it can replace the current PLIC. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>	2020-06-19 08:24:07 -07:00