803963f7cb
target/riscv: rvv: Add tail agnostic for vector permutation instructions
...
Signed-off-by: eop Chen <eop.chen@sifive.com >
Reviewed-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn >
Acked-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <165449614532.19704.7000832880482980398-15@git.sr.ht >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-06-10 09:31:42 +10:00
acc6ffd482
target/riscv: rvv: Add tail agnostic for vector mask instructions
...
The tail elements in the destination mask register are updated under
a tail-agnostic policy.
Signed-off-by: eop Chen <eop.chen@sifive.com >
Reviewed-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn >
Acked-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <165449614532.19704.7000832880482980398-14@git.sr.ht >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-06-10 09:31:42 +10:00
df4f52a758
target/riscv: rvv: Add tail agnostic for vector reduction instructions
...
Signed-off-by: eop Chen <eop.chen@sifive.com >
Reviewed-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn >
Acked-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <165449614532.19704.7000832880482980398-13@git.sr.ht >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-06-10 09:31:42 +10:00
5eacf7d8a0
target/riscv: rvv: Add tail agnostic for vector floating-point instructions
...
Compares write mask registers, and so always operate under a tail-
agnostic policy.
Signed-off-by: eop Chen <eop.chen@sifive.com >
Reviewed-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn >
Acked-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <165449614532.19704.7000832880482980398-12@git.sr.ht >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-06-10 09:31:42 +10:00
09106eed30
target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic instructions
...
Signed-off-by: eop Chen <eop.chen@sifive.com >
Reviewed-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn >
Acked-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <165449614532.19704.7000832880482980398-11@git.sr.ht >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-06-10 09:31:42 +10:00
89a32de2d5
target/riscv: rvv: Add tail agnostic for vector integer merge and move instructions
...
Signed-off-by: eop Chen <eop.chen@sifive.com >
Reviewed-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn >
Acked-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <165449614532.19704.7000832880482980398-10@git.sr.ht >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-06-10 09:31:42 +10:00
38581e5c9a
target/riscv: rvv: Add tail agnostic for vector integer comparison instructions
...
Compares write mask registers, and so always operate under a tail-
agnostic policy.
Signed-off-by: eop Chen <eop.chen@sifive.com >
Reviewed-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn >
Acked-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <165449614532.19704.7000832880482980398-9@git.sr.ht >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-06-10 09:31:42 +10:00
7b1bff41c1
target/riscv: rvv: Add tail agnostic for vector integer shift instructions
...
Signed-off-by: eop Chen <eop.chen@sifive.com >
Reviewed-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn >
Acked-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <165449614532.19704.7000832880482980398-8@git.sr.ht >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-06-10 09:31:42 +10:00
5c19fc156e
target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions
...
`vmadc` and `vmsbc` produces a mask value, they always operate with
a tail agnostic policy.
Signed-off-by: eop Chen <eop.chen@sifive.com >
Reviewed-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn >
Acked-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <165449614532.19704.7000832880482980398-7@git.sr.ht >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-06-10 09:31:42 +10:00
752614cab8
target/riscv: rvv: Add tail agnostic for vector load / store instructions
...
Destination register of unit-stride mask load and store instructions are
always written with a tail-agnostic policy.
A vector segment load / store instruction may contain fractional lmul
with nf * lmul > 1. The rest of the elements in the last register should
be treated as tail elements.
Signed-off-by: eop Chen <eop.chen@sifive.com >
Reviewed-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn >
Acked-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <165449614532.19704.7000832880482980398-6@git.sr.ht >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-06-10 09:31:42 +10:00
f1eed927fb
target/riscv: rvv: Add tail agnostic for vv instructions
...
According to v-spec, tail agnostic behavior can be either kept as
undisturbed or set elements' bits to all 1s. To distinguish the
difference of tail policies, QEMU should be able to simulate the tail
agnostic behavior as "set tail elements' bits to all 1s".
There are multiple possibility for agnostic elements according to
v-spec. The main intent of this patch-set tries to add option that
can distinguish between tail policies. Setting agnostic elements to
all 1s allows QEMU to express this.
This is the first commit regarding the optional tail agnostic
behavior. Follow-up commits will add this optional behavior
for all rvv instructions.
Signed-off-by: eop Chen <eop.chen@sifive.com >
Reviewed-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn >
Acked-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <165449614532.19704.7000832880482980398-5@git.sr.ht >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-06-10 09:31:42 +10:00
c7b8a4213b
target/riscv: rvv: Rename ambiguous esz
...
No functional change intended in this commit.
Signed-off-by: eop Chen <eop.chen@sifive.com >
Reviewed-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <165449614532.19704.7000832880482980398-3@git.sr.ht >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-06-10 09:31:42 +10:00
25eae0486d
target/riscv: rvv: Prune redundant access_type parameter passed
...
No functional change intended in this commit.
Signed-off-by: eop Chen <eop.chen@sifive.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <165449614532.19704.7000832880482980398-2@git.sr.ht >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-06-10 09:31:42 +10:00
8a085fb2ad
target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed
...
No functional change intended in this commit.
Signed-off-by: eop Chen <eop.chen@sifive.com >
Reviewed-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <165449614532.19704.7000832880482980398-1@git.sr.ht >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-06-10 09:31:42 +10:00
f06193c40b
target/riscv: fix start byte for vmv<nf>r.v when vstart != 0
...
The spec for vmv<nf>r.v says: 'the instructions operate as if EEW=SEW,
EMUL = NREG, effective length evl= EMUL * VLEN/SEW.'
So the start byte for vstart != 0 should take sew into account
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn >
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn >
Acked-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20220330021316.18223-1-liweiwei@iscas.ac.cn >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-04-22 10:35:16 +10:00
f32d82f6c3
target/riscv: optimize helper for vmv<nr>r.v
...
LEN is not used for GEN_VEXT_VMV_WHOLE macro, so vmv<nr>r.v can share
the same helper
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn >
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn >
Reviewed-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20220325085902.29500-2-liweiwei@iscas.ac.cn >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-04-22 10:35:16 +10:00
e03b56863d
Replace config-time define HOST_WORDS_BIGENDIAN
...
Replace a config-time define with a compile time condition
define (compatible with clang and gcc) that must be declared prior to
its usage. This avoids having a global configure time define, but also
prevents from bad usage, if the config header wasn't included before.
This can help to make some code independent from qemu too.
gcc supports __BYTE_ORDER__ from about 4.6 and clang from 3.2.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com >
[ For the s390x parts I'm involved in ]
Acked-by: Halil Pasic <pasic@linux.ibm.com >
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20220323155743.1585078-7-marcandre.lureau@redhat.com >
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com >
2022-04-06 10:50:37 +02:00
ac6bcf4d46
target/riscv: Fix vill field write in vtype
...
The guest should be able to set the vill bit as part of vsetvl.
Currently we may set env->vill to 1 in the vsetvl helper, but there
is nowhere that we set it to 0, so once it transitions to 1 it's stuck
there until the system is reset.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20220201064601.41143-1-zhiwei_liu@c-sky.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-02-16 12:24:18 +10:00
d6b9d93023
target/riscv: Adjust vector address with mask
...
The mask comes from the pointer masking extension, or the max value
corresponding to XLEN bits.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com >
Acked-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20220120122050.41546-20-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-01-21 15:52:57 +10:00
01d09525da
target/riscv: Fix check range for first fault only
...
Only check the range that has passed the address translation.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20220120122050.41546-19-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-01-21 15:52:57 +10:00
31961cfe50
target/riscv: Adjust vsetvl according to XLEN
...
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20220120122050.41546-17-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-01-21 15:52:57 +10:00
d96a271a8d
target/riscv: Split out the vill from vtype
...
We need not specially process vtype when XLEN changes.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20220120122050.41546-16-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-01-21 15:52:57 +10:00
9c0d2559de
target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm
...
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20211210075704.23951-76-frank.chang@sifive.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-12-20 14:53:31 +10:00
26086aea0d
target/riscv: rvv-1.0: add vector unit-stride mask load/store insns
...
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Acked-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20211210075704.23951-75-frank.chang@sifive.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-12-20 14:53:31 +10:00
5c89e9c096
target/riscv: rvv-1.0: add evl parameter to vext_ldst_us()
...
Add supports of Vector unit-stride mask load/store instructions
(vlm.v, vsm.v), which has:
evl (effective vector length) = ceil(env->vl / 8).
The new instructions operate the same as unmasked byte loads and stores.
Add evl parameter to reuse vext_ldst_us().
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20211210075704.23951-74-frank.chang@sifive.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-12-20 14:53:31 +10:00
55c35407c3
target/riscv: rvv-1.0: floating-point reciprocal estimate instruction
...
Implement the floating-point reciprocal estimate to 7 bits instruction.
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Acked-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20211210075704.23951-71-frank.chang@sifive.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-12-20 14:53:31 +10:00
e848a1e563
target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction
...
Implement the floating-point reciprocal square-root estimate to 7 bits
instruction.
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Acked-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20211210075704.23951-70-frank.chang@sifive.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-12-20 14:53:31 +10:00
f714361ed7
target/riscv: rvv-1.0: implement vstart CSR
...
* Update and check vstart value for vector instructions.
* Add whole register move instruction helper functions as we have to
call helper function for case where vstart is not zero.
* Remove probe_pages() calls in vector load/store instructions
(except fault-only-first loads) to raise the memory access exception
at the exact processed vector element.
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20211210075704.23951-67-frank.chang@sifive.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-12-20 14:53:31 +10:00
8a4b52575a
target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits
...
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20211210075704.23951-66-frank.chang@sifive.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-12-20 14:53:31 +10:00
ff679b58e3
target/riscv: rvv-1.0: narrowing floating-point/integer type-convert
...
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Acked-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20211210075704.23951-65-frank.chang@sifive.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-12-20 14:53:31 +10:00
3ce4c09df7
target/riscv: rvv-1.0: widening floating-point/integer type-convert
...
Add the following instructions:
* vfwcvt.rtz.xu.f.v
* vfwcvt.rtz.x.f.v
Also adjust GEN_OPFV_WIDEN_TRANS() to accept multiple floating-point
rounding modes.
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Acked-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20211210075704.23951-63-frank.chang@sifive.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-12-20 14:53:31 +10:00
49c5611a97
target/riscv: rvv-1.0: floating-point min/max instructions
...
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20211210075704.23951-60-frank.chang@sifive.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-12-20 14:53:31 +10:00
e29c5cefd8
target/riscv: rvv-1.0: remove vmford.vv and vmford.vf
...
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20211210075704.23951-58-frank.chang@sifive.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-12-20 14:53:31 +10:00
a12c812d19
target/riscv: rvv-1.0: remove widening saturating scaled multiply-add
...
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20211210075704.23951-57-frank.chang@sifive.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-12-20 14:53:31 +10:00
08b60eebc4
target/riscv: rvv-1.0: single-width floating-point reduction
...
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20211210075704.23951-54-frank.chang@sifive.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-12-20 14:53:31 +10:00
a70b3a73e7
target/riscv: rvv-1.0: narrowing fixed-point clip instructions
...
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20211210075704.23951-53-frank.chang@sifive.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-12-20 14:53:31 +10:00
8500d4ab2e
target/riscv: rvv-1.0: floating-point slide instructions
...
Add the following instructions:
* vfslide1up.vf
* vfslide1down.vf
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20211210075704.23951-52-frank.chang@sifive.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-12-20 14:53:31 +10:00
6438ed61de
target/riscv: rvv-1.0: slide instructions
...
* Remove clear function from helper functions as the tail elements
are unchanged in RVV 1.0.
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20211210075704.23951-51-frank.chang@sifive.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-12-20 14:53:22 +10:00
50f6696c0f
target/riscv: rvv-1.0: mask-register logical instructions
...
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20211210075704.23951-50-frank.chang@sifive.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-12-20 14:51:36 +10:00
e70aa16e5e
target/riscv: rvv-1.0: floating-point compare instructions
...
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20211210075704.23951-49-frank.chang@sifive.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-12-20 14:51:36 +10:00
063f8bbca0
target/riscv: rvv-1.0: integer comparison instructions
...
* Sign-extend vmselu.vi and vmsgtu.vi immediate values.
* Remove "set tail elements to zeros" as tail elements can be unchanged
for either VTA to have undisturbed or agnostic setting.
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20211210075704.23951-48-frank.chang@sifive.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-12-20 14:51:36 +10:00
7daa5852bc
target/riscv: rvv-1.0: narrowing integer right shift instructions
...
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20211210075704.23951-45-frank.chang@sifive.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-12-20 14:51:36 +10:00
bb45485ad1
target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow
...
* Only do carry-in or borrow-in if is masked (vm=0).
* Remove clear function from helper functions as the tail elements
are unchanged in RVV 1.0.
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20211210075704.23951-44-frank.chang@sifive.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-12-20 14:51:36 +10:00
8b99a110f7
target/riscv: rvv-1.0: single-width averaging add and subtract instructions
...
Add the following instructions:
* vaaddu.vv
* vaaddu.vx
* vasubu.vv
* vasubu.vx
Remove the following instructions:
* vadd.vi
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20211210075704.23951-42-frank.chang@sifive.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-12-20 14:51:36 +10:00
cd01340e75
target/riscv: rvv-1.0: integer extension instructions
...
Add the following instructions:
* vzext.vf2
* vzext.vf4
* vzext.vf8
* vsext.vf2
* vsext.vf4
* vsext.vf8
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20211210075704.23951-41-frank.chang@sifive.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-12-20 14:51:36 +10:00
50bfb45b2c
target/riscv: rvv-1.0: register gather instructions
...
* Add vrgatherei16.vv instruction.
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20211210075704.23951-36-frank.chang@sifive.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-12-20 14:51:36 +10:00
40c1495d69
target/riscv: rvv-1.0: set-X-first mask bit instructions
...
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20211210075704.23951-32-frank.chang@sifive.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-12-20 14:51:36 +10:00
d71a24fc82
target/riscv: rvv-1.0: find-first-set mask bit instruction
...
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20211210075704.23951-31-frank.chang@sifive.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-12-20 14:51:36 +10:00
0014aa741d
target/riscv: rvv-1.0: count population in mask instruction
...
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20211210075704.23951-30-frank.chang@sifive.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-12-20 14:51:36 +10:00
5a9f8e1552
target/riscv: rvv-1.0: update vext_max_elems() for load/store insns
...
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20211210075704.23951-26-frank.chang@sifive.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-12-20 14:51:36 +10:00
