3780e33732
target/riscv: Support mcycle/minstret write operation
...
mcycle/minstret are actually WARL registers and can be written with any
given value. With SBI PMU extension, it will be used to store a initial
value provided from supervisor OS. The Qemu also need prohibit the counter
increment if mcountinhibit is set.
Support mcycle/minstret through generic counter infrastructure.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Atish Patra <atish.patra@wdc.com >
Signed-off-by: Atish Patra <atishp@rivosinc.com >
Message-Id: <20220620231603.2547260-8-atishp@rivosinc.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-07-03 10:03:20 +10:00
621f35bb2f
target/riscv: Add support for hpmcounters/hpmevents
...
With SBI PMU extension, user can use any of the available hpmcounters to
track any perf events based on the value written to mhpmevent csr.
Add read/write functionality for these csrs.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Signed-off-by: Atish Patra <atish.patra@wdc.com >
Signed-off-by: Atish Patra <atishp@rivosinc.com >
Message-Id: <20220620231603.2547260-7-atishp@rivosinc.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-07-03 10:03:20 +10:00
b1675eeb3e
target/riscv: Implement mcountinhibit CSR
...
As per the privilege specification v1.11, mcountinhibit allows to start/stop
a pmu counter selectively.
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Atish Patra <atish.patra@wdc.com >
Signed-off-by: Atish Patra <atishp@rivosinc.com >
Message-Id: <20220620231603.2547260-6-atishp@rivosinc.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-07-03 10:03:20 +10:00
38b4e781a4
target/riscv: machine: Add debug state description
...
Add a subsection to machine.c to migrate debug CSR state.
Signed-off-by: Bin Meng <bin.meng@windriver.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20220421003324.1134983-5-bmeng.cn@gmail.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-04-22 10:35:16 +10:00
29a9ec9bd8
target/riscv: Add *envcfg* CSRs support
...
The RISC-V privileged specification v1.12 defines few execution
environment configuration CSRs that can be used enable/disable
extensions per privilege levels.
Add the basic support for these CSRs.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Atish Patra <atishp@rivosinc.com >
Message-Id: <20220303185440.512391-6-atishp@rivosinc.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-04-22 10:35:16 +10:00
d1ceff405a
target/riscv: Implement AIA xiselect and xireg CSRs
...
The AIA specification defines [m|s|vs]iselect and [m|s|vs]ireg CSRs
which allow indirect access to interrupt priority arrays and per-HART
IMSIC registers. This patch implements AIA xiselect and xireg CSRs.
Signed-off-by: Anup Patel <anup.patel@wdc.com >
Signed-off-by: Anup Patel <anup@brainfault.org >
Reviewed-by: Frank Chang <frank.chang@sifive.com >
Message-id: 20220204174700.534953-15-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-02-16 12:24:19 +10:00
2b60239879
target/riscv: Implement AIA hvictl and hviprioX CSRs
...
The AIA hvictl and hviprioX CSRs allow hypervisor to control
interrupts visible at VS-level. This patch implements AIA hvictl
and hviprioX CSRs.
Signed-off-by: Anup Patel <anup.patel@wdc.com >
Signed-off-by: Anup Patel <anup@brainfault.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Frank Chang <frank.chang@sifive.com >
Message-id: 20220204174700.534953-12-anup@brainfault.org
[ Changes by AF:
- Fix possible unintilised variable error in rmw_sie()
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-02-16 12:24:19 +10:00
d028ac7512
target/riscv: Implement AIA CSRs for 64 local interrupts on RV32
...
The AIA specification adds new CSRs for RV32 so that RISC-V hart can
support 64 local interrupts on both RV32 and RV64.
Signed-off-by: Anup Patel <anup.patel@wdc.com >
Signed-off-by: Anup Patel <anup@brainfault.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Frank Chang <frank.chang@sifive.com >
Message-id: 20220204174700.534953-11-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-02-16 12:24:19 +10:00
43dc93af36
target/riscv: Implement AIA local interrupt priorities
...
The AIA spec defines programmable 8-bit priority for each local interrupt
at M-level, S-level and VS-level so we extend local interrupt processing
to consider AIA interrupt priorities. The AIA CSRs which help software
configure local interrupt priorities will be added by subsequent patches.
Signed-off-by: Anup Patel <anup.patel@wdc.com >
Signed-off-by: Anup Patel <anup@brainfault.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20220204174700.534953-10-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-02-16 12:24:19 +10:00
cd032fe75c
target/riscv: Implement hgeie and hgeip CSRs
...
The hgeie and hgeip CSRs are required for emulating an external
interrupt controller capable of injecting virtual external interrupt
to Guest/VM running at VS-level.
Signed-off-by: Anup Patel <anup.patel@wdc.com >
Signed-off-by: Anup Patel <anup@brainfault.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Frank Chang <frank.chang@sifive.com >
Message-id: 20220204174700.534953-4-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-02-16 12:24:18 +10:00
d96a271a8d
target/riscv: Split out the vill from vtype
...
We need not specially process vtype when XLEN changes.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20220120122050.41546-16-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-01-21 15:52:57 +10:00
40bfa5f695
target/riscv: Create current pm fields in env
...
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20220120122050.41546-12-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-01-21 15:52:57 +10:00
440544e1cf
target/riscv: Create xl field in env
...
Current xlen has been used in helper functions and many other places.
The computation of current xlen is not so trivial, so that we should
recompute it as little as possible.
Fortunately, xlen only changes in very seldom cases, such as exception,
misa write, mstatus write, cpu reset, migration load. So that we can only
recompute xlen in this places and cache it into CPURISCVState.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20220120122050.41546-6-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-01-21 15:52:57 +10:00
1eb9a5da31
target/riscv: Support virtual time context synchronization
...
Add virtual time context description to vmstate_kvmtimer. After cpu being
loaded, virtual time context is updated to KVM.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com >
Signed-off-by: Mingwang Li <limingwang@huawei.com >
Reviewed-by: Anup Patel <anup.patel@wdc.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20220112081329.1835-13-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-01-21 15:52:56 +10:00
2c64ab66c1
target/riscv: adding high part of some csrs
...
Adding the high part of a very minimal set of csr.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr >
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20220106210108.138226-16-frederic.petrot@univ-grenoble-alpes.fr
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-01-08 15:46:10 +10:00
2b5470843a
target/riscv: array for the 64 upper bits of 128-bit registers
...
The upper 64-bit of the 128-bit registers have now a place inside
the cpu state structure, and are created as globals for future use.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr >
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20220106210108.138226-7-frederic.petrot@univ-grenoble-alpes.fr
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-01-08 15:46:10 +10:00
edcc4e4090
target/riscv: machine: Sort the .subsections
...
Move the codes around so that the order of .subsections matches
the one they are referenced in vmstate_riscv_cpu.
Signed-off-by: Bin Meng <bin.meng@windriver.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20211030030606.32297-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-11-17 19:18:22 +10:00
b1c279e135
target/riscv: Add J extension state description
...
Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20211025173609.2724490-5-space.monkey.delivers@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-10-28 14:39:23 +10:00
e91a7227cb
target/riscv: Split misa.mxl and misa.ext
...
The hw representation of misa.mxl is at the high bits of the
misa csr. Representing this in the same way inside QEMU
results in overly complex code trying to check that field.
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20211020031709.359469-4-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-10-22 07:47:51 +10:00
ac12b60103
target/riscv: Remove privilege v1.9 specific CSR related code
...
Qemu doesn't support RISC-V privilege specification v1.9. Remove the
remaining v1.9 specific references from the implementation.
Signed-off-by: Atish Patra <atish.patra@wdc.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20210319194534.2082397-2-atish.patra@wdc.com >
[Changes by AF:
- Rebase on latest patches
- Bump the vmstate_riscv_cpu version_id and minimum_version_id
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-05-11 20:01:10 +10:00
bb02edcd86
target/riscv: Add V extension state description
...
In the case of supporting V extension, add V extension description
to vmstate_riscv_cpu.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com >
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20201026115530.304-6-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2020-11-03 07:17:23 -08:00
35e07821ff
target/riscv: Add H extension state description
...
In the case of supporting H extension, add H extension description
to vmstate_riscv_cpu.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com >
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20201026115530.304-5-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2020-11-03 07:17:23 -08:00
24beb03e46
target/riscv: Add PMP state description
...
In the case of supporting PMP feature, add PMP state description
to vmstate_riscv_cpu.
'vmstate_pmp_addr' and 'num_rules' could be regenerated by
pmp_update_rule(). But there exists the problem of updating
num_rules repeatedly in pmp_update_rule(). So here extracts
pmp_update_rule_addr() and pmp_update_rule_nums() to update
'vmstate_pmp_addr' and 'num_rules' respectively.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com >
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20201026115530.304-4-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2020-11-03 07:17:23 -08:00
f7697f0e62
target/riscv: Add basic vmstate description of CPU
...
Add basic CPU state description to the newly created machine.c
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com >
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20201026115530.304-3-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2020-11-03 07:17:23 -08:00
