52581c718c
Clean up header guards that don't match their file name
...
Header guard symbols should match their file name to make guard
collisions less likely.
Cleaned up with scripts/clean-header-guards.pl, followed by some
renaming of new guard symbols picked by the script to better ones.
Signed-off-by: Markus Armbruster <armbru@redhat.com >
Message-Id: <20220506134911.2856099-2-armbru@redhat.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
[Change to generated file ebpf/rss.bpf.skeleton.h backed out]
2022-05-11 16:49:06 +02:00
1832b7cb3f
hw/riscv: virt: Create a platform bus
...
Create a platform bus to allow dynamic devices to be connected. This is
based on the ARM implementation.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Message-Id: <20220427234146.1130752-4-alistair.francis@opensource.wdc.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-04-29 10:48:31 +10:00
1c20d3ff60
hw/riscv: virt: Add a machine done notifier
...
Move the binary and device tree loading code to the machine done
notifier. This allows us to prepare for editing the device tree as part
of the notifier.
This is based on similar code in the ARM virt machine.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Message-Id: <20220427234146.1130752-2-alistair.francis@opensource.wdc.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-04-29 10:48:12 +10:00
faee5441a0
hw/riscv: boot: Support 64bit fdt address.
...
The current riscv_load_fdt() forces fdt_load_addr to be placed at a dram address within 3GB,
but not all platforms have dram_base within 3GB.
This patch adds an exception for dram base not within 3GB,
which will place fdt at dram_end align 16MB.
riscv_setup_rom_reset_vec() also needs to be modified
Signed-off-by: Dylan Jhong <dylan@andestech.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20220419115945.37945-1-dylan@andestech.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-04-22 10:35:16 +10:00
9972479fac
riscv: opentitan: Connect opentitan SPI Host
...
Connect spi host[1/0] to opentitan.
Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Message-Id: <20220303045426.511588-2-alistair.francis@opensource.wdc.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-04-22 10:35:16 +10:00
aecabd50b7
hw: riscv: opentitan: fixup SPI addresses
...
This patch updates the SPI_DEVICE, SPI_HOST0, SPI_HOST1
base addresses. Also adds these as unimplemented devices.
The address references can be found [1].
[1] 6c317992fb/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h (L107)wilfred.mallawa@wdc.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Message-Id: <20220218063839.405082-1-alistair.francis@opensource.wdc.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-03-03 13:14:50 +10:00
0631aaae31
hw/riscv: virt: Increase maximum number of allowed CPUs
...
To facilitate software development of RISC-V systems with large number
of HARTs, we increase the maximum number of allowed CPUs to 512 (2^9).
We also add a detailed source level comments about limit defines which
impact the physical address space utilization.
Signed-off-by: Anup Patel <anup.patel@wdc.com >
Signed-off-by: Anup Patel <anup@brainfault.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Frank Chang <frank.chang@sifive.com >
Message-Id: <20220220085526.808674-6-anup@brainfault.org >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-03-03 13:14:50 +10:00
28d8c28120
hw/riscv: virt: Add optional AIA IMSIC support to virt machine
...
We extend virt machine to emulate both AIA IMSIC and AIA APLIC
devices only when "aia=aplic-imsic" parameter is passed along
with machine name in the QEMU command-line. The AIA IMSIC is
only a per-HART MSI controller so we use AIA APLIC in MSI-mode
to forward all wired interrupts as MSIs to the AIA IMSIC.
We also provide "aia-guests=<xyz>" parameter which can be used
to specify number of VS-level AIA IMSIC Guests MMIO pages for
each HART.
Signed-off-by: Anup Patel <anup.patel@wdc.com >
Signed-off-by: Anup Patel <anup@brainfault.org >
Acked-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20220220085526.808674-4-anup@brainfault.org >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-03-03 13:14:50 +10:00
e6faee6585
hw/riscv: virt: Add optional AIA APLIC support to virt machine
...
We extend virt machine to emulate AIA APLIC devices only when
"aia=aplic" parameter is passed along with machine name in QEMU
command-line. When "aia=none" or not specified then we fallback
to original PLIC device emulation.
Signed-off-by: Anup Patel <anup.patel@wdc.com >
Signed-off-by: Anup Patel <anup@brainfault.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20220220085526.808674-2-anup@brainfault.org >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-03-03 13:14:50 +10:00
092dc6df92
hw/riscv: Remove macros for ELF BIOS image names
...
Now that RISC-V Spike machine can use BIN BIOS images, we remove
the macros used for ELF BIOS image names.
Signed-off-by: Anup Patel <apatel@ventanamicro.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-01-21 15:52:57 +10:00
8d8897accb
hw/riscv: spike: Allow using binary firmware as bios
...
Currently, we have to use OpenSBI firmware ELF as bios for the spike
machine because the HTIF console requires ELF for parsing "fromhost"
and "tohost" symbols.
The latest OpenSBI can now optionally pick-up HTIF register address
from HTIF DT node so using this feature spike machine can now use
OpenSBI firmware BIN as bios.
Signed-off-by: Anup Patel <apatel@ventanamicro.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-01-21 15:52:56 +10:00
ad40be2708
target/riscv: Support start kernel directly by KVM
...
Get kernel and fdt start address in virt.c, and pass them to KVM
when cpu reset. Add kvm_riscv.h to place riscv specific interface.
In addition, PLIC is created without M-mode PLIC contexts when KVM
is enabled.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com >
Signed-off-by: Mingwang Li <limingwang@huawei.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Anup Patel <anup@brainfault.org >
Message-id: 20220112081329.1835-7-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-01-21 15:52:56 +10:00
d4452c6924
hw/riscv: virt: Allow support for 32 cores
...
Linux supports up to 32 cores for both 32-bit and 64-bit RISC-V, so
let's set that as the maximum for the virt board.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/435
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Anup Patel <anup.patel@wdc.com >
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Message-Id: <20220105213937.1113508-9-alistair.francis@opensource.wdc.com >
2022-01-08 15:46:09 +10:00
8486eb8cdc
hw/riscv: microchip_pfsoc: Use the PLIC config helper function
...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Tested-by: Bin Meng <bmeng.cn@gmail.com >
Message-id: 20211022060133.3045020-4-alistair.francis@opensource.wdc.com
2021-10-28 14:39:23 +10:00
4e8fb53c0b
hw/riscv: sifive_u: Use the PLIC config helper function
...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Tested-by: Bin Meng <bmeng.cn@gmail.com >
Message-id: 20211022060133.3045020-3-alistair.francis@opensource.wdc.com
2021-10-28 14:39:23 +10:00
bf357e1d72
hw/riscv: boot: Add a PLIC config string function
...
Add a generic function that can create the PLIC strings.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Message-id: 20211022060133.3045020-2-alistair.francis@opensource.wdc.com
2021-10-28 14:39:23 +10:00
9925c8bb81
hw/riscv: virt: Don't use a macro for the PLIC configuration
...
Using a macro for the PLIC configuration doesn't make the code any
easier to read. Instead it makes it harder to figure out what is going
on, so let's remove it.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Message-id: 20211022060133.3045020-1-alistair.francis@opensource.wdc.com
2021-10-28 14:39:23 +10:00
ef63100648
hw/riscv: opentitan: Update to the latest build
...
Update the OpenTitan machine model to match the latest OpenTitan FPGA
design.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Message-id: 18b1b681b0f8dd2461e819d1217bf0b530812680.1634524691.git.alistair.francis@wdc.com
2021-10-22 23:35:47 +10:00
954886ea6d
hw/riscv: virt: Add optional ACLINT support to virt machine
...
We extend virt machine to emulate ACLINT devices only when "aclint=on"
parameter is passed along with machine name in QEMU command-line.
Signed-off-by: Anup Patel <anup.patel@wdc.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Message-id: 20210831110603.338681-5-anup.patel@wdc.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-09-21 07:56:49 +10:00
ea6eaa0604
sifive_u: Connect the SiFive PWM device
...
Connect the SiFive PWM device and expose it via the device tree.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Message-id: 22f98648b4e012f78529a56f5ca60b0b27852a4d.1631159656.git.alistair.francis@wdc.com
2021-09-21 07:56:49 +10:00
bb7e0cde3c
hw/riscv: opentitan: Add the flash alias
...
OpenTitan has an alias of flash avaliable which is called virtual flash.
Add support for that in the QEMU model.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Message-id: c9cfbd2dd840fd0076877b8ea4d6dcfce60db5e9.1625801868.git.alistair.francis@wdc.com
2021-07-15 08:56:00 +10:00
5ee257649f
hw/riscv: opentitan: Add the unimplement rv_core_ibex_peri
...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Message-id: ed707782e84118e1b06a32fd79b70fecfb54ff82.1625801868.git.alistair.francis@wdc.com
2021-07-15 08:56:00 +10:00
3ef6434409
hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer
...
Connect the Ibex timer to the OpenTitan machine. The timer can trigger
the RISC-V MIE interrupt as well as a custom device interrupt.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Message-id: 5e7f4e9b4537f863bcb8db1264b840b56ef2a929.1624001156.git.alistair.francis@wdc.com
2021-06-24 05:00:13 -07:00
a0acd0a175
hw/riscv: Use macros for BIOS image names
...
The OpenSBI BIOS image names are used by many RISC-V machines.
Let's define macros for them.
Signed-off-by: Bin Meng <bin.meng@windriver.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20210430071302.1489082-7-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-06-08 09:59:42 +10:00
d4cad54499
hw/opentitan: Update the interrupt layout
...
Update the OpenTitan interrupt layout to match the latest OpenTitan
bitstreams. This involves changing the Ibex PLIC memory layout and the
UART interrupts.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Message-id: e92b696f1809c9fa4410da2e9f23c414db5a6960.1617202791.git.alistair.francis@wdc.com
2021-05-11 20:02:06 +10:00
8a2aca3d79
hw/riscv: Connect Shakti UART to Shakti platform
...
Connect one shakti uart to the shakti_c machine.
Signed-off-by: Vijai Kumar K <vijai@behindbytes.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20210401181457.73039-5-vijai@behindbytes.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-05-11 20:02:06 +10:00
7a261bafc8
riscv: Add initial support for Shakti C machine
...
Add support for emulating Shakti reference platform based on C-class
running on arty-100T board.
https://gitlab.com/shaktiproject/cores/shakti-soc/-/blob/master/README.rst
Signed-off-by: Vijai Kumar K <vijai@behindbytes.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20210401181457.73039-3-vijai@behindbytes.com
[Changes by AF:
- Check for mstate->firmware before loading it
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-05-11 20:01:38 +10:00
d6150ace2b
hw/riscv: microchip_pfsoc: Map EMMC/SD mux register
...
Since HSS commit c20a89f8dcac, the Icicle Kit reference design has
been updated to use a register mapped at 0x4f000000 instead of a
GPIO to control whether eMMC or SD card is to be used. With this
support the same HSS image can be used for both eMMC and SD card
boot flow, while previously two different board configurations were
used. This is undocumented but one can take a look at the HSS code
HSS_MMCInit() in services/mmc/mmc_api.c.
With this commit, HSS image built from 2020.12 release boots again.
Signed-off-by: Bin Meng <bin.meng@windriver.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20210322075248.136255-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-03-22 21:54:40 -04:00
0489348d0d
hw/riscv: Add fw_cfg support to virt
...
Provides fw_cfg for the virt machine on riscv. This enables
using e.g. ramfb later.
Signed-off-by: Asherah Connor <ashe@kivikakk.ee >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20210318235041.17175-2-ashe@kivikakk.ee
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-03-22 21:54:40 -04:00
c65d7080d8
hw/riscv: migrate fdt field to generic MachineState
...
This is a mechanical change to make the fdt available through
MachineState.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com >
Message-Id: <20210303173642.3805-3-alex.bennee@linaro.org >
2021-03-10 15:34:11 +00:00
8e3c886870
hw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal value
...
All other peripherals' IRQs are in the format of decimal value.
Change SIFIVE_U_GEM_IRQ to be consistent.
Signed-off-by: Bin Meng <bin.meng@windriver.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20210126060007.12904-7-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-03-04 09:43:29 -05:00
722f1352b6
hw/riscv: sifive_u: Add QSPI2 controller and connect an SD card
...
This adds the QSPI2 controller to the SoC, and connects an SD
card to it. The generation of corresponding device tree source
fragment is also added.
Specify machine property `msel` to 11 to boot the same upstream
U-Boot SPL and payload image for the SiFive HiFive Unleashed board.
Note subsequent payload is stored in the SD card image.
$ qemu-system-riscv64 -nographic -M sifive_u,msel=11 -smp 5 -m 8G \
-bios u-boot-spl.bin -drive file=sdcard.img,if=sd
Signed-off-by: Bin Meng <bin.meng@windriver.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20210126060007.12904-6-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-03-04 09:43:29 -05:00
145b299139
hw/riscv: sifive_u: Add QSPI0 controller and connect a flash
...
This adds the QSPI0 controller to the SoC, and connects an ISSI
25WP256 flash to it. The generation of corresponding device tree
source fragment is also added.
Since the direct memory-mapped mode is not supported by the SiFive
SPI model, the <reg> property does not populate the second group
which represents the memory mapped address of the SPI flash.
With this commit, upstream U-Boot for the SiFive HiFive Unleashed
board can boot on QEMU 'sifive_u' out of the box. This allows users
to develop and test the recommended RISC-V boot flow with a real
world use case: ZSBL (in QEMU) loads U-Boot SPL from SPI flash to
L2LIM, then U-Boot SPL loads the payload from SPI flash that is
combined with OpenSBI fw_dynamic firmware and U-Boot proper.
Specify machine property `msel` to 6 to allow booting from the SPI
flash. U-Boot spl is directly loaded via `-bios`, and subsequent
payload is stored in the SPI flash image. Example command line:
$ qemu-system-riscv64 -nographic -M sifive_u,msel=6 -smp 5 -m 8G \
-bios u-boot-spl.bin -drive file=spi-nor.img,if=mtd
Signed-off-by: Bin Meng <bin.meng@windriver.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20210126060007.12904-5-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-03-04 09:43:29 -05:00
a8259b5323
riscv: Pass RISCVHartArrayState by pointer
...
We were accidently passing RISCVHartArrayState by value instead of
pointer. The type is 824 bytes long so let's correct that and pass it by
pointer instead.
Fixes: Coverity CID 1438099
Fixes: Coverity CID 1438100
Fixes: Coverity CID 1438101
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com >
Reviewed-by: Bin Meng <bin.meng@windriver.com >
Message-id: f3e04424723e0e222769991896cc82308fd23f76.1610751609.git.alistair.francis@wdc.com
2021-01-16 14:34:46 -08:00
d31e970a01
riscv/opentitan: Update the OpenTitan memory layout
...
OpenTitan is currently only avalible on an FPGA platform and the memory
addresses have changed. Update to use the new memory addresses.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 8eb65314830a75d0fea3fccf77bc45b8ddd01c42.1607982831.git.alistair.francis@wdc.com
2020-12-17 21:56:44 -08:00
3ed2b8ac2d
hw/riscv: Use the CPU to determine if 32-bit
...
Instead of using string compares to determine if a RISC-V machine is
using 32-bit or 64-bit CPUs we can use the initalised CPUs. This avoids
us having to maintain a list of CPU names to compare against.
This commit also fixes the name of the function to match the
riscv_cpu_is_32bit() function.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 8ab7614e5df93ab5267788b73dcd75f9f5615e82.1608142916.git.alistair.francis@wdc.com
2020-12-17 21:56:44 -08:00
7893677184
hw/riscv: boot: Remove compile time XLEN checks
...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Bin Meng <bin.meng@windriver.com >
Tested-by: Bin Meng <bin.meng@windriver.com >
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com >
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com >
Message-id: 51e9842dbed1acceebad7f97bd3aae69aa1ac19e.1608142916.git.alistair.francis@wdc.com
2020-12-17 21:56:44 -08:00
09fe17125e
riscv: virt: Remove target macro conditionals
...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Bin Meng <bin.meng@windriver.com >
Tested-by: Bin Meng <bin.meng@windriver.com >
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com >
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com >
Message-id: aed1174c2efd2f050fa5bd8f524d68795b12c0e4.1608142916.git.alistair.francis@wdc.com
2020-12-17 21:56:44 -08:00
dc4d4aaee3
riscv: spike: Remove target macro conditionals
...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Bin Meng <bin.meng@windriver.com >
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com >
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com >
Message-id: 04ac7fba2348c92f296a5e6a9959ac72b77ae4c6.1608142916.git.alistair.francis@wdc.com
2020-12-17 21:56:44 -08:00
dfc973ecc1
hw/riscv: microchip_pfsoc: add QSPI NOR flash
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Add QSPI NOR flash definition for Microchip PolarFire SoC.
Signed-off-by: Vitaly Wool <vitaly.wool@konsulko.com >
Acked-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Bin Meng <bin.meng@windriver.com >
Message-id: 20201112074950.33283-1-vitaly.wool@konsulko.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2020-12-17 21:56:43 -08:00
90742c5496
hw/riscv: microchip_pfsoc: Hook the I2C1 controller
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The latest SD card image [1] released by Microchip ships a Linux
kernel with built-in PolarFire SoC I2C driver support. The device
tree file includes the description for the I2C1 node hence kernel
tries to probe the I2C1 device during boot.
It is enough to create an unimplemented device for I2C1 to allow
the kernel to continue booting to the shell.
[1] ftp://ftpsoc.microsemi.com/outgoing/core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic.gz
Signed-off-by: Bin Meng <bin.meng@windriver.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 1603863010-15807-11-git-send-email-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2020-11-03 07:17:23 -08:00
f03100d718
hw/riscv: microchip_pfsoc: Correct DDR memory map
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When system memory is larger than 1 GiB (high memory), PolarFire SoC
maps it at address 0x10_0000_0000. Address 0xC000_0000 and above is
aliased to the same 1 GiB low memory with different cache attributes.
At present QEMU maps the system memory contiguously from 0x8000_0000.
This corrects the wrong QEMU logic. Note address 0x14_0000_0000 is
the alias to the high memory, and even physical memory is only 1 GiB,
the HSS codes still tries to probe the high memory alias address.
It seems there is no issue on the real hardware, so we will have to
take that into the consideration in our emulation. Due to this, we
we increase the default system memory size to 1537 MiB (the minimum
required high memory size by HSS) so that user gets notified an error
when less than 1537 MiB is specified.
Signed-off-by: Bin Meng <bin.meng@windriver.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20201101170538.3732-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2020-11-03 07:17:23 -08:00
27c22b2de0
hw/riscv: microchip_pfsoc: Map the reserved memory at address 0
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Somehow HSS needs to access address 0 [1] for the DDR calibration data
which is in the chipset's reserved memory. Let's map it.
[1] See the config_copy() calls in various places in ddr_setup() in
the HSS source codes.
Signed-off-by: Bin Meng <bin.meng@windriver.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 1603863010-15807-9-git-send-email-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2020-11-03 07:17:23 -08:00
cdd58c70fb
hw/riscv: microchip_pfsoc: Connect the SYSREG module
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Previously SYSREG was created as an unimplemented device. Now that
we have a simple SYSREG module, connect it.
Signed-off-by: Bin Meng <bin.meng@windriver.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 1603863010-15807-8-git-send-email-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2020-11-03 07:17:23 -08:00
e35d617919
hw/riscv: microchip_pfsoc: Connect the IOSCB module
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Previously IOSCB_CFG was created as an unimplemented device. With
the new IOSCB model, its memory range is already covered by the
IOSCB hence remove the previous unimplemented device creation in
the SoC codes.
Signed-off-by: Bin Meng <bin.meng@windriver.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 1603863010-15807-6-git-send-email-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2020-11-03 07:17:23 -08:00
933f73f13e
hw/riscv: microchip_pfsoc: Connect DDR memory controller modules
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Connect DDR SGMII PHY module and CFG module to the PolarFire SoC.
Signed-off-by: Bin Meng <bin.meng@windriver.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 1603863010-15807-4-git-send-email-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2020-11-03 07:17:23 -08:00
38bc4e34f2
hw/riscv: Load the kernel after the firmware
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Instead of loading the kernel at a hardcoded start address, let's load
the kernel at the next aligned address after the end of the firmware.
This should have no impact for current users of OpenSBI, but will
allow loading a noMMU kernel at the start of memory.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com >
Reviewed-by: Bin Meng <bin.meng@windriver.com >
Tested-by: Bin Meng <bin.meng@windriver.com >
Message-id: 46c00c4f15b42feb792090e3d74359e180a6d954.1602634524.git.alistair.francis@wdc.com
2020-10-22 12:00:22 -07:00
c407784291
hw/riscv: Add a riscv_is_32_bit() function
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com >
Reviewed-by: Bin Meng <bin.meng@windriver.com >
Tested-by: Bin Meng <bin.meng@windriver.com >
Message-id: 4c6a85dfb6dd470aa79356ebc1b02f479c2758e0.1602634524.git.alistair.francis@wdc.com
2020-10-22 12:00:22 -07:00
e66c531e13
hw/riscv: Return the end address of the loaded firmware
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Instead of returning the unused entry address from riscv_load_firmware()
instead return the end address. Also return the end address from
riscv_find_and_load_firmware().
This tells the caller if a firmware was loaded and how big it is. This
can be used to determine the load address of the next image (usually the
kernel).
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com >
Reviewed-by: Bin Meng <bin.meng@windriver.com >
Tested-by: Bin Meng <bin.meng@windriver.com >
Message-id: 558cf67162342d65a23262248b040563716628b2.1602634524.git.alistair.francis@wdc.com
2020-10-22 12:00:22 -07:00
099be0358e
hw/riscv: sifive_u: Allow specifying the CPU
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Allow the user to specify the main application CPU for the sifive_u
machine.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Bin Meng <bin.meng@windriver.com >
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com >
Tested-by: Bin Meng <bin.meng@windriver.com >
Message-id: b8412086c8aea0eff30fb7a17f0acf2943381b6a.1602634524.git.alistair.francis@wdc.com
2020-10-22 12:00:22 -07:00
