a8259b5323
riscv: Pass RISCVHartArrayState by pointer
...
We were accidently passing RISCVHartArrayState by value instead of
pointer. The type is 824 bytes long so let's correct that and pass it by
pointer instead.
Fixes: Coverity CID 1438099
Fixes: Coverity CID 1438100
Fixes: Coverity CID 1438101
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com >
Reviewed-by: Bin Meng <bin.meng@windriver.com >
Message-id: f3e04424723e0e222769991896cc82308fd23f76.1610751609.git.alistair.francis@wdc.com
2021-01-16 14:34:46 -08:00
1eaada8ae1
hw/riscv: sifive_u: Use SIFIVE_U_CPU for mc->default_cpu_type
...
SIFIVE_U_CPU is conditionally set to SIFIVE_U34 or SIFIVE_U54, hence
there is no need to use #idef to set the mc->default_cpu_type.
Signed-off-by: Bin Meng <bin.meng@windriver.com >
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20210109143637.29645-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-01-16 10:57:21 -08:00
1a475d39ef
RISC-V: Place DTB at 3GB boundary instead of 4GB
...
Currently, we place the DTB at 2MB from 4GB or end of DRAM which ever is
lesser. However, Linux kernel can address only 1GB of memory for RV32.
Thus, it can not map anything beyond 3GB (assuming 2GB is the starting address).
As a result, it can not process DT and panic if opensbi dynamic firmware
is used. While at it, place the DTB further away to avoid in memory placement
issues in future.
Fix this by placing the DTB at 16MB from 3GB or end of DRAM whichever is lower.
Fixes: 66b1205bc5bin.meng@windriver.com >
Tested-by: Bin Meng <bin.meng@windriver.com >
Signed-off-by: Atish Patra <atish.patra@wdc.com >
Message-id: 20210107091127.3407870-1-atish.patra@wdc.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-01-16 10:57:21 -08:00
d31e970a01
riscv/opentitan: Update the OpenTitan memory layout
...
OpenTitan is currently only avalible on an FPGA platform and the memory
addresses have changed. Update to use the new memory addresses.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 8eb65314830a75d0fea3fccf77bc45b8ddd01c42.1607982831.git.alistair.francis@wdc.com
2020-12-17 21:56:44 -08:00
3ed2b8ac2d
hw/riscv: Use the CPU to determine if 32-bit
...
Instead of using string compares to determine if a RISC-V machine is
using 32-bit or 64-bit CPUs we can use the initalised CPUs. This avoids
us having to maintain a list of CPU names to compare against.
This commit also fixes the name of the function to match the
riscv_cpu_is_32bit() function.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 8ab7614e5df93ab5267788b73dcd75f9f5615e82.1608142916.git.alistair.francis@wdc.com
2020-12-17 21:56:44 -08:00
2206ffa68f
hw/riscv: sifive_u: Remove compile time XLEN checks
...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com >
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com >
Reviewed-by: Bin Meng <bin.meng@windriver.com >
Tested-by: Bin Meng <bin.meng@windriver.com >
Message-id: 40d6df4dd05302c566e419be3a1fef7799e57c2e.1608142916.git.alistair.francis@wdc.com
2020-12-17 21:56:44 -08:00
bd62c13ea8
hw/riscv: spike: Remove compile time XLEN checks
...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Bin Meng <bin.meng@windriver.com >
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com >
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com >
Message-id: ac75037dd58061486de421a0fcd9ac8a92014607.1608142916.git.alistair.francis@wdc.com
2020-12-17 21:56:44 -08:00
9d01143063
hw/riscv: virt: Remove compile time XLEN checks
...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Bin Meng <bin.meng@windriver.com >
Tested-by: Bin Meng <bin.meng@windriver.com >
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com >
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com >
Message-id: d7ca1aca672515e6a4aa0d41716238b055f3f25c.1608142916.git.alistair.francis@wdc.com
2020-12-17 21:56:44 -08:00
7893677184
hw/riscv: boot: Remove compile time XLEN checks
...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Bin Meng <bin.meng@windriver.com >
Tested-by: Bin Meng <bin.meng@windriver.com >
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com >
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com >
Message-id: 51e9842dbed1acceebad7f97bd3aae69aa1ac19e.1608142916.git.alistair.francis@wdc.com
2020-12-17 21:56:44 -08:00
09fe17125e
riscv: virt: Remove target macro conditionals
...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Bin Meng <bin.meng@windriver.com >
Tested-by: Bin Meng <bin.meng@windriver.com >
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com >
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com >
Message-id: aed1174c2efd2f050fa5bd8f524d68795b12c0e4.1608142916.git.alistair.francis@wdc.com
2020-12-17 21:56:44 -08:00
dc4d4aaee3
riscv: spike: Remove target macro conditionals
...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Bin Meng <bin.meng@windriver.com >
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com >
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com >
Message-id: 04ac7fba2348c92f296a5e6a9959ac72b77ae4c6.1608142916.git.alistair.francis@wdc.com
2020-12-17 21:56:44 -08:00
617448a46b
hw/riscv: Expand the is 32-bit check to support more CPUs
...
Currently the riscv_is_32_bit() function only supports the generic rv32
CPUs. Extend the function to support the SiFive and LowRISC CPUs as
well.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com >
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com >
Message-id: 9a13764115ba78688ba61b56526c6de65fc3ef42.1608142916.git.alistair.francis@wdc.com
2020-12-17 21:56:43 -08:00
dfc973ecc1
hw/riscv: microchip_pfsoc: add QSPI NOR flash
...
Add QSPI NOR flash definition for Microchip PolarFire SoC.
Signed-off-by: Vitaly Wool <vitaly.wool@konsulko.com >
Acked-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Bin Meng <bin.meng@windriver.com >
Message-id: 20201112074950.33283-1-vitaly.wool@konsulko.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2020-12-17 21:56:43 -08:00
10b43754cf
hw/riscv: sifive_u: Add UART1 DT node in the generated DTB
...
The sifive_u machine emulates two UARTs but we have only UART0 DT
node in the generated DTB so this patch adds UART1 DT node in the
generated DTB.
Signed-off-by: Anup Patel <anup.patel@wdc.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20201111094725.3768755-1-anup.patel@wdc.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2020-12-17 21:56:43 -08:00
f2ce39b4f0
vl: make qemu_get_machine_opts static
...
Machine options can be retrieved as properties of the machine object.
Encourage that by removing the "easy" accessor to machine options.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com >
2020-12-15 12:51:55 -05:00
2c65db5e58
vl: extract softmmu/datadir.c
...
Reviewed-by: Igor Mammedov <imammedo@redhat.com >
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com >
2020-12-10 12:15:18 -05:00
82e6905465
riscv: do not use ram_size global
...
Use the machine properties instead.
Cc: Alistair Francis <Alistair.Francis@wdc.com >
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com >
2020-12-10 12:15:09 -05:00
90742c5496
hw/riscv: microchip_pfsoc: Hook the I2C1 controller
...
The latest SD card image [1] released by Microchip ships a Linux
kernel with built-in PolarFire SoC I2C driver support. The device
tree file includes the description for the I2C1 node hence kernel
tries to probe the I2C1 device during boot.
It is enough to create an unimplemented device for I2C1 to allow
the kernel to continue booting to the shell.
[1] ftp://ftpsoc.microsemi.com/outgoing/core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic.gz
Signed-off-by: Bin Meng <bin.meng@windriver.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 1603863010-15807-11-git-send-email-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2020-11-03 07:17:23 -08:00
f03100d718
hw/riscv: microchip_pfsoc: Correct DDR memory map
...
When system memory is larger than 1 GiB (high memory), PolarFire SoC
maps it at address 0x10_0000_0000. Address 0xC000_0000 and above is
aliased to the same 1 GiB low memory with different cache attributes.
At present QEMU maps the system memory contiguously from 0x8000_0000.
This corrects the wrong QEMU logic. Note address 0x14_0000_0000 is
the alias to the high memory, and even physical memory is only 1 GiB,
the HSS codes still tries to probe the high memory alias address.
It seems there is no issue on the real hardware, so we will have to
take that into the consideration in our emulation. Due to this, we
we increase the default system memory size to 1537 MiB (the minimum
required high memory size by HSS) so that user gets notified an error
when less than 1537 MiB is specified.
Signed-off-by: Bin Meng <bin.meng@windriver.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20201101170538.3732-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2020-11-03 07:17:23 -08:00
27c22b2de0
hw/riscv: microchip_pfsoc: Map the reserved memory at address 0
...
Somehow HSS needs to access address 0 [1] for the DDR calibration data
which is in the chipset's reserved memory. Let's map it.
[1] See the config_copy() calls in various places in ddr_setup() in
the HSS source codes.
Signed-off-by: Bin Meng <bin.meng@windriver.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 1603863010-15807-9-git-send-email-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2020-11-03 07:17:23 -08:00
cdd58c70fb
hw/riscv: microchip_pfsoc: Connect the SYSREG module
...
Previously SYSREG was created as an unimplemented device. Now that
we have a simple SYSREG module, connect it.
Signed-off-by: Bin Meng <bin.meng@windriver.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 1603863010-15807-8-git-send-email-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2020-11-03 07:17:23 -08:00
e35d617919
hw/riscv: microchip_pfsoc: Connect the IOSCB module
...
Previously IOSCB_CFG was created as an unimplemented device. With
the new IOSCB model, its memory range is already covered by the
IOSCB hence remove the previous unimplemented device creation in
the SoC codes.
Signed-off-by: Bin Meng <bin.meng@windriver.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 1603863010-15807-6-git-send-email-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2020-11-03 07:17:23 -08:00
933f73f13e
hw/riscv: microchip_pfsoc: Connect DDR memory controller modules
...
Connect DDR SGMII PHY module and CFG module to the PolarFire SoC.
Signed-off-by: Bin Meng <bin.meng@windriver.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 1603863010-15807-4-git-send-email-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2020-11-03 07:17:23 -08:00
08b86e3b8f
hw/riscv: microchip_pfsoc: Document where to look at the SoC memory maps
...
It is not easy to find out the memory map for a specific component
in the PolarFire SoC as the information is scattered in different
documents. Add some comments so that people can know where to get
such information from the Microchip website.
Signed-off-by: Bin Meng <bin.meng@windriver.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 1603863010-15807-2-git-send-email-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2020-11-03 07:17:23 -08:00
4e1e3003fb
hw/riscv: virt: Allow passing custom DTB
...
Extend virt machine to allow passing custom DTB using "-dtb"
command-line parameter. This will help users pass modified DTB
to virt machine.
Signed-off-by: Anup Patel <anup.patel@wdc.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20201022053225.2596110-2-anup.patel@wdc.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2020-11-03 07:17:23 -08:00
d5c90cf3f6
hw/riscv: sifive_u: Allow passing custom DTB
...
Extend sifive_u machine to allow passing custom DTB using "-dtb"
command-line parameter. This will help users pass modified DTB
or Linux SiFive DTB to sifive_u machine.
Signed-off-by: Anup Patel <anup.patel@wdc.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20201022053225.2596110-1-anup.patel@wdc.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2020-11-03 07:17:23 -08:00
38bc4e34f2
hw/riscv: Load the kernel after the firmware
...
Instead of loading the kernel at a hardcoded start address, let's load
the kernel at the next aligned address after the end of the firmware.
This should have no impact for current users of OpenSBI, but will
allow loading a noMMU kernel at the start of memory.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com >
Reviewed-by: Bin Meng <bin.meng@windriver.com >
Tested-by: Bin Meng <bin.meng@windriver.com >
Message-id: 46c00c4f15b42feb792090e3d74359e180a6d954.1602634524.git.alistair.francis@wdc.com
2020-10-22 12:00:22 -07:00
c407784291
hw/riscv: Add a riscv_is_32_bit() function
...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com >
Reviewed-by: Bin Meng <bin.meng@windriver.com >
Tested-by: Bin Meng <bin.meng@windriver.com >
Message-id: 4c6a85dfb6dd470aa79356ebc1b02f479c2758e0.1602634524.git.alistair.francis@wdc.com
2020-10-22 12:00:22 -07:00
e66c531e13
hw/riscv: Return the end address of the loaded firmware
...
Instead of returning the unused entry address from riscv_load_firmware()
instead return the end address. Also return the end address from
riscv_find_and_load_firmware().
This tells the caller if a firmware was loaded and how big it is. This
can be used to determine the load address of the next image (usually the
kernel).
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com >
Reviewed-by: Bin Meng <bin.meng@windriver.com >
Tested-by: Bin Meng <bin.meng@windriver.com >
Message-id: 558cf67162342d65a23262248b040563716628b2.1602634524.git.alistair.francis@wdc.com
2020-10-22 12:00:22 -07:00
099be0358e
hw/riscv: sifive_u: Allow specifying the CPU
...
Allow the user to specify the main application CPU for the sifive_u
machine.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Bin Meng <bin.meng@windriver.com >
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com >
Tested-by: Bin Meng <bin.meng@windriver.com >
Message-id: b8412086c8aea0eff30fb7a17f0acf2943381b6a.1602634524.git.alistair.francis@wdc.com
2020-10-22 12:00:22 -07:00
617160c9e1
load_elf: Remove unused address variables from callers
...
Several callers of load_elf() pass pointers for lowaddr and highaddr
parameters which are then not used for anything. This may stem from a
misunderstanding that load_elf need a value here but in fact it can
take NULL to ignore these values. Remove such unused variables and
pass NULL instead from callers that don't need these.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu >
Reviewed-by: David Gibson <david@gibson.dropbear.id.au >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Acked-by: David Gibson <david@gibson.dropbear.id.au >
Acked-by: Max Filippov <jcmvbkbc@gmail.com >
Message-Id: <20200705174020.BDD0174633F@zero.eik.bme.hu >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2020-09-25 16:52:08 -07:00
418b473e8f
sifive_u: Register "start-in-flash" as class property
...
Class properties make QOM introspection simpler and easier, as
they don't require an object to be instantiated.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20200921221045.699690-25-ehabkost@redhat.com >
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com >
2020-09-22 16:48:29 -04:00
fabbcbd953
sifive_e: Register "revb" as class property
...
Class properties make QOM introspection simpler and easier, as
they don't require an object to be instantiated.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20200921221045.699690-24-ehabkost@redhat.com >
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com >
2020-09-22 16:48:29 -04:00
13b8c35418
sifive_u: Rename memmap enum constants
...
Some of the enum constant names conflict with the QOM type check
macros (SIFIVE_U_OTP, SIFIVE_U_PRCI). This needs to be addressed
to allow us to transform the QOM type check macros into functions
generated by OBJECT_DECLARE_TYPE().
Rename all the constants to SIFIVE_U_DEV_*, to avoid conflicts.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20200911173447.165713-3-ehabkost@redhat.com >
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com >
2020-09-18 13:49:48 -04:00
5488f2760a
sifive_e: Rename memmap enum constants
...
Some of the enum constant names conflict with a QOM type check
macro (SIFIVE_E_PRCI). This needs to be addressed to allow us to
transform the QOM type check macros into functions generated by
OBJECT_DECLARE_TYPE().
Rename all the constants to SIFIVE_E_DEV_*, to avoid conflicts.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20200911173447.165713-2-ehabkost@redhat.com >
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com >
2020-09-18 13:49:48 -04:00
7595a65818
hw/riscv: Sort the Kconfig options in alphabetical order
...
At present the Kconfig file is in disorder. Let's sort the options.
Signed-off-by: Bin Meng <bin.meng@windriver.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <1599129623-68957-13-git-send-email-bmeng.cn@gmail.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2020-09-09 15:54:19 -07:00
4791b4c4ab
hw/riscv: Drop CONFIG_SIFIVE
...
The name SIFIVE is too vague to convey the required component of
MSI_NONBROKEN. Let's drop the option, and select MSI_NONBROKEN in
each machine instead.
Signed-off-by: Bin Meng <bin.meng@windriver.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <1599129623-68957-12-git-send-email-bmeng.cn@gmail.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2020-09-09 15:54:19 -07:00
30a4af1664
hw/riscv: Always build riscv_hart.c
...
Every RISC-V machine needs riscv_hart hence there is no need to
have a dedicated Kconfig option for it. Drop the Kconfig option
and always build riscv_hart.c.
Signed-off-by: Bin Meng <bin.meng@windriver.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <1599129623-68957-11-git-send-email-bmeng.cn@gmail.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2020-09-09 15:54:19 -07:00
a4b84608ba
hw/riscv: Move sifive_test model to hw/misc
...
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_test model to hw/misc directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <1599129623-68957-10-git-send-email-bmeng.cn@gmail.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2020-09-09 15:54:19 -07:00
b609b7e319
hw/riscv: Move sifive_uart model to hw/char
...
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_uart model to hw/char directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <1599129623-68957-9-git-send-email-bmeng.cn@gmail.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2020-09-09 15:54:19 -07:00
70eb9f9cd1
hw/riscv: Move riscv_htif model to hw/char
...
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move riscv_htif model to hw/char directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <1599129623-68957-8-git-send-email-bmeng.cn@gmail.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2020-09-09 15:54:19 -07:00
84fcf3c151
hw/riscv: Move sifive_plic model to hw/intc
...
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_plic model to hw/intc directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <1599129623-68957-7-git-send-email-bmeng.cn@gmail.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2020-09-09 15:54:19 -07:00
406fafd5d0
hw/riscv: Move sifive_clint model to hw/intc
...
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_clint model to hw/intc directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <1599129623-68957-6-git-send-email-bmeng.cn@gmail.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2020-09-09 15:54:19 -07:00
4921a0ce86
hw/riscv: Move sifive_gpio model to hw/gpio
...
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_gpio model to hw/gpio directory.
Note this also removes the trace-events in the hw/riscv directory,
since gpio is the only supported trace target in that directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <1599129623-68957-5-git-send-email-bmeng.cn@gmail.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2020-09-09 15:54:19 -07:00
0fa9e32945
hw/riscv: Move sifive_u_otp model to hw/misc
...
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_u_otp model to hw/misc directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <1599129623-68957-4-git-send-email-bmeng.cn@gmail.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2020-09-09 15:54:19 -07:00
9fe640a53d
hw/riscv: Move sifive_u_prci model to hw/misc
...
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_u_prci model to hw/misc directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <1599129623-68957-3-git-send-email-bmeng.cn@gmail.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2020-09-09 15:54:19 -07:00
89ece6f76f
hw/riscv: Move sifive_e_prci model to hw/misc
...
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_e_prci model to hw/misc directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <1599129623-68957-2-git-send-email-bmeng.cn@gmail.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2020-09-09 15:54:19 -07:00
834e027a34
hw/riscv: sifive_u: Connect a DMA controller
...
SiFive FU540 SoC integrates a platform DMA controller with 4 DMA
channels. This connects the exsiting SiFive PDMA model to the SoC,
and adds its device tree data as well.
Signed-off-by: Bin Meng <bin.meng@windriver.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <1598924352-89526-17-git-send-email-bmeng.cn@gmail.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2020-09-09 15:54:19 -07:00
a47ef6e93a
hw/riscv: clint: Avoid using hard-coded timebase frequency
...
At present the CLINT timestamp is using a hard-coded timebase
frequency value SIFIVE_CLINT_TIMEBASE_FREQ. This might not be
true for all boards.
Add a new 'timebase-freq' property to the CLINT device, and
update various functions to accept this as a parameter.
Signed-off-by: Bin Meng <bin.meng@windriver.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <1598924352-89526-16-git-send-email-bmeng.cn@gmail.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2020-09-09 15:54:19 -07:00
ce908a2f6f
hw/riscv: microchip_pfsoc: Hook GPIO controllers
...
Microchip PolarFire SoC integrates 3 GPIOs controllers. It seems
enough to create unimplemented devices to cover their register
spaces at this point.
With this commit, QEMU can boot to U-Boot (2nd stage bootloader)
all the way to the Linux shell login prompt, with a modified HSS
(1st stage bootloader).
For detailed instructions on how to create images for the Icicle
Kit board, please check QEMU RISC-V WiKi page at:
https://wiki.qemu.org/Documentation/Platforms/RISCV
Signed-off-by: Bin Meng <bin.meng@windriver.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Message-Id: <1598924352-89526-15-git-send-email-bmeng.cn@gmail.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2020-09-09 15:54:19 -07:00
