5 Commits

Author	SHA1	Message	Date
Leon Alrae	c09199fe73	hw/mips_cmgcr: implement RESET_BASE register in CM GCR ... Implement RESET_BASE register which is local to each VP and a write to it changes VP's reset exception base. Also, add OTHER register to allow a software running on one VP to access other VP's local registers. Guest can use this mechanism to specify custom address from which a VP will start execution. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>	2016-07-12 09:10:16 +01:00
Leon Alrae	19494f811a	hw/mips/cps: create GIC block inside CPS ... Add GIC to CPS and expose its interrupt pins instead of CPU's. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>	2016-07-12 09:10:13 +01:00
Paolo Bonzini	03dd024ff5	hw: explicitly include qemu/log.h ... Move the inclusion out of hw/hw.h, most files do not need it. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>	2016-05-19 16:42:29 +02:00
Leon Alrae	2edd5261ff	hw/mips/cps: create CPC block inside CPS ... Create Cluster Power Controller and add a link to the CPC MemoryRegion in GCR. Guest can enable / map CPC to any physical address by writing to the memory-mapped GCR_CPC_BASE register. Set vp-start-reset property to 1 to allow only first VP to run from reset. Others are brought up by the guest via CPC memory-mapped registers. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>	2016-03-30 09:13:59 +01:00
Yongbok Kim	3994215db4	hw/mips: add initial Global Config Register support ... Add initial GCR support to indicate number of VPs present in the system, L2 bypass mode and revision number. Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> [leon.alrae@imgtec.com: * removed GIC part, * changed commit message, * replaced %lx format spec. with PRIx64, * renamed mips_gcr.{c,h} to mips_cmgcr.{c,h}, * replaced CONFIG_MIPS_GIC with CONFIG_MIPS_CPS] Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>	2016-03-30 09:13:59 +01:00