02369f7906
target/riscv: Introduce mmuidx_2stage
...
Move and rename riscv_cpu_two_stage_lookup, to match
the other mmuidx_* functions.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn >
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com >
Message-Id: <20230325105429.1142530-15-richard.henderson@linaro.org >
Message-Id: <20230412114333.118895-15-richard.henderson@linaro.org >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-05-05 10:49:50 +10:00
340b5805db
target/riscv: Introduce mmuidx_priv
...
Use the priv level encoded into the mmu_idx, rather than
starting from env->priv. We have already checked MPRV+MPP
in riscv_cpu_mmu_index -- no need to repeat that.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn >
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com >
Message-Id: <20230325105429.1142530-14-richard.henderson@linaro.org >
Message-Id: <20230412114333.118895-14-richard.henderson@linaro.org >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-05-05 10:49:50 +10:00
4005a799f1
target/riscv: Introduce mmuidx_sum
...
In get_physical_address, we should use the setting passed
via mmu_idx rather than checking env->mstatus directly.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn >
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com >
Message-Id: <20230325105429.1142530-13-richard.henderson@linaro.org >
Message-Id: <20230412114333.118895-13-richard.henderson@linaro.org >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-05-05 10:49:50 +10:00
3df44173e9
target/riscv: Rename MMU_HYP_ACCESS_BIT to MMU_2STAGE_BIT
...
We will enable more uses of this bit in the future.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn >
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com >
Message-Id: <20230325105429.1142530-12-richard.henderson@linaro.org >
Message-Id: <20230412114333.118895-12-richard.henderson@linaro.org >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-05-05 10:49:50 +10:00
c8f8a9957e
target/riscv: Reduce overhead of MSTATUS_SUM change
...
Kernel needs to access user mode memory e.g. during syscalls, the window
is usually opened up for a very limited time through MSTATUS.SUM, the
overhead is too much if tlb_flush() gets called for every SUM change.
This patch creates a separate MMU index for S+SUM, so that it's not
necessary to flush tlb anymore when SUM changes. This is similar to how
ARM handles Privileged Access Never (PAN).
Result of 'pipe 10' from unixbench boosts from 223656 to 1705006. Many
other syscalls benefit a lot from this too.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: Fei Wu <fei2.wu@intel.com >
Message-Id: <20230324054154.414846-3-fei2.wu@intel.com >
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn >
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com >
Message-Id: <20230325105429.1142530-8-richard.henderson@linaro.org >
Message-Id: <20230412114333.118895-8-richard.henderson@linaro.org >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-05-05 10:49:50 +10:00
355d5584de
target/riscv: rvv: Add mask agnostic for vv instructions
...
According to v-spec, mask agnostic behavior can be either kept as
undisturbed or set elements' bits to all 1s. To distinguish the
difference of mask policies, QEMU should be able to simulate the mask
agnostic behavior as "set mask elements' bits to all 1s".
There are multiple possibility for agnostic elements according to
v-spec. The main intent of this patch-set tries to add option that
can distinguish between mask policies. Setting agnostic elements to
all 1s allows QEMU to express this.
This is the first commit regarding the optional mask agnostic
behavior. Follow-up commits will add this optional behavior
for all rvv instructions.
Signed-off-by: eop Chen <eop.chen@sifive.com >
Reviewed-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <165570784143.17634.35095816584573691-1@git.sr.ht >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-09-07 09:18:32 +02:00
5c19fc156e
target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions
...
`vmadc` and `vmsbc` produces a mask value, they always operate with
a tail agnostic policy.
Signed-off-by: eop Chen <eop.chen@sifive.com >
Reviewed-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn >
Acked-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <165449614532.19704.7000832880482980398-7@git.sr.ht >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-06-10 09:31:42 +10:00
f1eed927fb
target/riscv: rvv: Add tail agnostic for vv instructions
...
According to v-spec, tail agnostic behavior can be either kept as
undisturbed or set elements' bits to all 1s. To distinguish the
difference of tail policies, QEMU should be able to simulate the tail
agnostic behavior as "set tail elements' bits to all 1s".
There are multiple possibility for agnostic elements according to
v-spec. The main intent of this patch-set tries to add option that
can distinguish between tail policies. Setting agnostic elements to
all 1s allows QEMU to express this.
This is the first commit regarding the optional tail agnostic
behavior. Follow-up commits will add this optional behavior
for all rvv instructions.
Signed-off-by: eop Chen <eop.chen@sifive.com >
Reviewed-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn >
Acked-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <165449614532.19704.7000832880482980398-5@git.sr.ht >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-06-10 09:31:42 +10:00
a2464a4cec
target/riscv: add support for zhinx/zhinxmin
...
- update extension check REQUIRE_ZHINX_OR_ZFH and REQUIRE_ZFH_OR_ZFHMIN_OR_ZHINX_OR_ZHINXMIN
- update half float point register read/write
- disable nanbox_h check
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn >
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Acked-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20220211043920.28981-6-liweiwei@iscas.ac.cn >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-03-03 13:14:50 +10:00
e1a29bbd54
target/riscv: add support for zfinx
...
- update extension check REQUIRE_ZFINX_OR_F
- update single float point register read/write
- disable nanbox_s check
Co-authored-by: ardxwe <ardxwe@gmail.com >
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn >
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Acked-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20220211043920.28981-4-liweiwei@iscas.ac.cn >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-03-03 13:14:50 +10:00
75804f7131
target/riscv: add "set round to odd" rounding mode helper function
...
helper_set_rounding_mode() is responsible for SIGILL, and "round to odd"
should be an interface private to translation, so add a new independent
helper_set_rod_rounding_mode().
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Acked-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20211210075704.23951-64-frank.chang@sifive.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-12-20 14:53:31 +10:00
986c895de1
target/riscv: introduce floating-point rounding mode enum
...
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20211210075704.23951-61-frank.chang@sifive.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-12-20 14:53:31 +10:00
5c4eb8fb56
target/riscv: rvv-1.0: floating-point scalar move instructions
...
NaN-boxed the scalar floating-point register based on RVV 1.0's rules.
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Acked-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20211210075704.23951-39-frank.chang@sifive.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-12-20 14:51:36 +10:00
f9298de514
target/riscv: rvv-1.0: remove MLEN calculations
...
As in RVV 1.0 design, MLEN is hardcoded with value 1 (Section 4.5).
Thus, remove all MLEN related calculations.
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20211210075704.23951-13-frank.chang@sifive.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-12-20 14:51:36 +10:00
00c1899f12
target/riscv: zfh: half-precision computational
...
Signed-off-by: Kito Cheng <kito.cheng@sifive.com >
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com >
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20211210074329.5775-3-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-12-20 14:51:36 +10:00
f7697f0e62
target/riscv: Add basic vmstate description of CPU
...
Add basic CPU state description to the newly created machine.c
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com >
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20201026115530.304-3-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2020-11-03 07:17:23 -08:00
00e925c560
target/riscv: Check nanboxed inputs to fp helpers
...
If a 32-bit input is not properly nanboxed, then the input is
replaced with the default qnan.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com >
Message-Id: <20200724002807.441147-5-richard.henderson@linaro.org >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2020-08-21 22:37:55 -07:00
9921e3d330
target/riscv: Generate nanboxed results from fp helpers
...
Make sure that all results from single-precision scalar helpers
are properly nan-boxed to 64-bits.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com >
Message-Id: <20200724002807.441147-2-richard.henderson@linaro.org >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2020-08-21 22:37:55 -07:00
9fc08be626
target/riscv: integer scalar move instruction
...
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20200701152549.1218-57-zhiwei_liu@c-sky.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2020-07-02 09:19:33 -07:00
121ddbb36f
target/riscv: vector floating-point classify instructions
...
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20200701152549.1218-41-zhiwei_liu@c-sky.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2020-07-02 09:19:33 -07:00
268fcca66b
target/riscv: add vector amo operations
...
Vector AMOs operate as if aq and rl bits were zero on each element
with regard to ordering relative to other instructions in the same hart.
Vector AMOs provide no ordering guarantee between element operations
in the same vector AMO instruction
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20200701152549.1218-10-zhiwei_liu@c-sky.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2020-07-02 09:19:33 -07:00
751538d5da
target/riscv: add vector stride load and store instructions
...
Vector strided operations access the first memory element at the base address,
and then access subsequent elements at address increments given by the byte
offset contained in the x register specified by rs2.
Vector unit-stride operations access elements stored contiguously in memory
starting from the base effective address. It can been seen as a special
case of strided operations.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20200701152549.1218-7-zhiwei_liu@c-sky.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2020-07-02 09:19:32 -07:00
f476f17740
target/riscv: add an internals.h header
...
The internals.h keeps things that are not relevant to the actual architecture,
only to the implementation, separate.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20200701152549.1218-6-zhiwei_liu@c-sky.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2020-07-02 09:19:32 -07:00
