022c7550d9
target/riscv: Change gen_set_pc_imm to gen_update_pc
...
Reduce reliance on absolute values(by passing pc difference) to
prepare for PC-relative translation.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn >
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20230526072124.298466-5-liweiwei@iscas.ac.cn >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-06-13 17:35:20 +10:00
47debc7280
target/riscv: Separate priv from mmu_idx
...
Currently it's assumed the 2 low bits of mmu_idx map to privilege mode,
this assumption won't last as we are about to add more mmu_idx. Here an
individual priv field is added into TB_FLAGS.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: Fei Wu <fei2.wu@intel.com >
Message-Id: <20230324054154.414846-2-fei2.wu@intel.com >
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn >
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com >
Message-Id: <20230325105429.1142530-7-richard.henderson@linaro.org >
Message-Id: <20230412114333.118895-7-richard.henderson@linaro.org >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-05-05 10:49:50 +10:00
f43442961e
target/riscv: Drop tcg_temp_free
...
Translators are no longer required to free tcg temporaries.
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn >
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2023-03-05 13:44:08 -08:00
b7fa70e2af
RISC-V: XTheadMemPair: Remove register restrictions for store-pair
...
The XTheadMemPair does not define any restrictions for store-pair
instructions (th.sdd or th.swd). However, the current code enforces
the restrictions that are required for load-pair instructions.
Let's fix this by removing this code.
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu >
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com >
Message-ID: <20230220095612.1529031-1-christoph.muellner@vrull.eu >
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com >
2023-03-01 16:59:50 -08:00
578086ba2f
RISC-V: Adding XTheadFmv ISA extension
...
This patch adds support for the XTheadFmv ISA extension.
The patch uses the T-Head specific decoder and translation.
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu >
Message-Id: <20230131202013.2541053-14-christoph.muellner@vrull.eu >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-02-07 08:19:23 +10:00
d4d901157e
RISC-V: Adding T-Head FMemIdx extension
...
This patch adds support for the T-Head FMemIdx instructions.
The patch uses the T-Head specific decoder and translation.
Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu >
Message-Id: <20230131202013.2541053-11-christoph.muellner@vrull.eu >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-02-07 08:19:23 +10:00
45f9df86db
RISC-V: Adding T-Head MemIdx extension
...
This patch adds support for the T-Head MemIdx instructions.
The patch uses the T-Head specific decoder and translation.
Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu >
Message-Id: <20230131202013.2541053-10-christoph.muellner@vrull.eu >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-02-07 08:19:23 +10:00
af99aa72ef
RISC-V: Adding T-Head MemPair extension
...
This patch adds support for the T-Head MemPair instructions.
The patch uses the T-Head specific decoder and translation.
Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu >
Message-Id: <20230131202013.2541053-9-christoph.muellner@vrull.eu >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-02-07 08:19:23 +10:00
b8a5832b87
RISC-V: Adding T-Head multiply-accumulate instructions
...
This patch adds support for the T-Head MAC instructions.
The patch uses the T-Head specific decoder and translation.
Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu >
Message-Id: <20230131202013.2541053-8-christoph.muellner@vrull.eu >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-02-07 08:19:23 +10:00
3290933853
RISC-V: Adding XTheadCondMov ISA extension
...
This patch adds support for the XTheadCondMov ISA extension.
The patch uses the T-Head specific decoder and translation.
Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu >
Message-Id: <20230131202013.2541053-7-christoph.muellner@vrull.eu >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-02-07 08:19:23 +10:00
fa13458546
RISC-V: Adding XTheadBs ISA extension
...
This patch adds support for the XTheadBs ISA extension.
The patch uses the T-Head specific decoder and translation.
Co-developed-by: Philipp Tomsich <philipp.tomsich@vrull.eu >
Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu >
Message-Id: <20230131202013.2541053-6-christoph.muellner@vrull.eu >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-02-07 08:19:23 +10:00
426c049196
RISC-V: Adding XTheadBb ISA extension
...
This patch adds support for the XTheadBb ISA extension.
The patch uses the T-Head specific decoder and translation.
Co-developed-by: Philipp Tomsich <philipp.tomsich@vrull.eu >
Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu >
Message-Id: <20230131202013.2541053-5-christoph.muellner@vrull.eu >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-02-07 08:19:23 +10:00
c9410a689f
RISC-V: Adding XTheadBa ISA extension
...
This patch adds support for the XTheadBa ISA extension.
The patch uses the T-Head specific decoder and translation.
Co-developed-by: Philipp Tomsich <philipp.tomsich@vrull.eu >
Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu >
Message-Id: <20230131202013.2541053-4-christoph.muellner@vrull.eu >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-02-07 08:19:23 +10:00
134c3ffa34
RISC-V: Adding XTheadSync ISA extension
...
This patch adds support for the XTheadSync ISA extension.
The patch uses the T-Head specific decoder and translation.
The implementation introduces a helper to execute synchronization tasks:
helper_tlb_flush_all() performs a synchronized TLB flush on all CPUs.
Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu >
Message-Id: <20230131202013.2541053-3-christoph.muellner@vrull.eu >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-02-07 08:19:23 +10:00
49a7f3aabb
RISC-V: Adding XTheadCmo ISA extension
...
This patch adds support for the XTheadCmo ISA extension.
To avoid interfering with standard extensions, decoder and translation
are in its own xthead* specific files.
Future patches should be able to easily add additional T-Head extension.
The implementation does not have much functionality (besides accepting
the instructions and not qualifying them as illegal instructions if
the hart executes in the required privilege level for the instruction),
as QEMU does not model CPU caches and instructions are documented
to not raise any exceptions.
Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com >
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20230131202013.2541053-2-christoph.muellner@vrull.eu >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-02-07 08:19:23 +10:00
