f43442961e
target/riscv: Drop tcg_temp_free
...
Translators are no longer required to free tcg temporaries.
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn >
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2023-03-05 13:44:08 -08:00
5fc0fc8788
target/riscv: fix ctzw behavior
...
According to spec, ctzw should work with 32-bit register, not 64.
For example, previous implementation returns 33 for (1<<33) input
when the new one returns 32.
Signed-off-by: Vladimir Isaev <vladimir.isaev@syntacore.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Suggested-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20230204082312.43557-1-vladimir.isaev@syntacore.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-02-07 08:19:23 +10:00
0496389680
target/riscv: rvk: add support for zbkx extension
...
- add xperm4 and xperm8 instructions
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn >
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Acked-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20220423023510.30794-5-liweiwei@iscas.ac.cn >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-04-29 10:47:45 +10:00
5cc69ceb68
target/riscv: rvk: add support for zbkc extension
...
- reuse partial instructions of zbc extension, update extension check for them
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn >
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20220423023510.30794-4-liweiwei@iscas.ac.cn >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-04-29 10:47:45 +10:00
d8e81e3c18
target/riscv: rvk: add support for zbkb extension
...
- reuse partial instructions of zbb extension, update extension check for them
- add brev8, pack, packh, packw, unzip, zip instructions
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn >
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn >
Acked-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20220423023510.30794-3-liweiwei@iscas.ac.cn >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-04-29 10:47:45 +10:00
90f9e35b78
target/riscv: fix inverted checks for ext_zb[abcs]
...
While changing to the use of cfg_ptr, the conditions for REQUIRE_ZB[ABCS]
inadvertently became inverted and slipped through the initial testing (which
used RV64GC_XVentanaCondOps as a target).
This fixes the regression.
Tested against SPEC2017 w/ GCC 12 (prerelease) for RV64GC_zba_zbb_zbc_zbs.
Fixes: f2a32bec8fphilipp.tomsich@vrull.eu >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20220203153946.2676353-1-philipp.tomsich@vrull.eu >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-03-03 13:14:50 +10:00
f2a32bec8f
target/riscv: access cfg structure through DisasContext
...
The Zb[abcs] support code still uses the RISCV_CPU macros to access
the configuration information (i.e., check whether an extension is
available/enabled). Now that we provide this information directly
from DisasContext, we can access this directly via the cfg_ptr field.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Suggested-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20220202005249.3566542-5-philipp.tomsich@vrull.eu >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-02-16 12:24:18 +10:00
7fd40f8679
target/riscv: support for 128-bit arithmetic instructions
...
Addition of 128-bit adds and subs in their various sizes,
"set if less than"s and branches.
Refactored the code to have a comparison function used for both stls and
branches.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr >
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20220106210108.138226-14-frederic.petrot@univ-grenoble-alpes.fr
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-01-08 15:46:10 +10:00
6bf4bbed20
target/riscv: support for 128-bit shift instructions
...
Handling shifts for 32, 64 and 128 operation length for RV128, following the
general framework for handling various olens proposed by Richard.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr >
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20220106210108.138226-13-frederic.petrot@univ-grenoble-alpes.fr
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-01-08 15:46:10 +10:00
a1a3aac448
target/riscv: separation of bitwise logic and arithmetic helpers
...
Introduction of a gen_logic function for bitwise logic to implement
instructions in which no propagation of information occurs between bits and
use of this function on the bitwise instructions.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr >
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20220106210108.138226-6-frederic.petrot@univ-grenoble-alpes.fr
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-01-08 15:46:10 +10:00
a0245d91dd
target/riscv: Use gen_shift*_per_ol for RVB, RVI
...
Most shift instructions require a separate implementation
for RV32 when TARGET_LONG_BITS == 64.
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20211020031709.359469-14-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-10-22 23:35:47 +10:00
fdab665f6e
target/riscv: Use gen_unary_per_ol for RVB
...
The count zeros instructions require a separate implementation
for RV32 when TARGET_LONG_BITS == 64.
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20211020031709.359469-13-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-10-22 23:35:47 +10:00
673be37163
target/riscv: Adjust trans_rev8_32 for riscv64
...
When target_long is 64-bit, we still want a 32-bit bswap for rev8.
Since this opcode is specific to RV32, we need not conditionalize.
Acked-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20211020031709.359469-12-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-10-22 23:35:47 +10:00
7667cafd5a
target/riscv: Replace DisasContext.w with DisasContext.ol
...
In preparation for RV128, consider more than just "w" for
operand size modification. This will be used for the "d"
insns from RV128 as well.
Rename oper_len to get_olen to better match get_xlen.
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20211020031709.359469-10-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-10-22 07:47:51 +10:00
54c1760937
target/riscv: Fix orc.b implementation
...
The earlier implementation fell into a corner case for bytes that were
0x01, giving a wrong result (but not affecting our application test
cases for strings, as an ASCII value 0x01 is rare in those...).
This changes the algorithm to:
1. Mask out the high-bit of each bytes (so that each byte is <= 127).
2. Add 127 to each byte (i.e. if the low 7 bits are not 0, this will overflow
into the highest bit of each byte).
3. Bitwise-or the original value back in (to cover those cases where the
source byte was exactly 128) to saturate the high-bit.
4. Shift-and-mask (implemented as a mask-and-shift) to extract the MSB of
each byte into its LSB.
5. Multiply with 0xff to fan out the LSB to all bits of each byte.
Fixes: d7a4fcb034philipp.tomsich@vrull.eu >
Reported-by: Vincent Palatin <vpalatin@rivosinc.com >
Tested-by: Vincent Palatin <vpalatin@rivosinc.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20211013184125.2010897-1-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-10-22 07:47:51 +10:00
06dfa8a5c5
target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh
...
The 1.0.0 version of Zbb does not contain pack/packu/packh. However, a
zext.h instruction is provided (built on pack/packh from pre-0.93
draft-B) is available.
This commit adds zext.h and removes the pack* instructions.
Note that the encodings for zext.h are different between RV32 and
RV64, which is handled through REQUIRE_32BIT.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20210911140016.834071-15-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-10-07 08:41:33 +10:00
a1095bdcb0
target/riscv: Add rev8 instruction, removing grev/grevi
...
The 1.0.0 version of Zbb does not contain grev/grevi. Instead, a
rev8 instruction (equivalent to the rev8 pseudo-instruction built on
grevi from pre-0.93 draft-B) is available.
This commit adds the new rev8 instruction and removes grev/grevi.
Note that there is no W-form of this instruction (both a
sign-extending and zero-extending 32-bit version can easily be
synthesized by following rev8 with either a srai or srli instruction
on RV64) and that the opcode encodings for rev8 in RV32 and RV64 are
different.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20210911140016.834071-14-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-10-07 08:41:33 +10:00
d7a4fcb034
target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci
...
The 1.0.0 version of Zbb does not contain gorc/gorci. Instead, a
orc.b instruction (equivalent to the orc.b pseudo-instruction built on
gorci from pre-0.93 draft-B) is available, mainly targeting
string-processing workloads.
This commit adds the new orc.b instruction and removed gorc/gorci.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20210911140016.834071-12-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-10-07 08:41:33 +10:00
16c38f36f5
target/riscv: Reassign instructions to the Zbb-extension
...
This reassigns the instructions that are part of Zbb into it, with the
notable exceptions of the instructions (rev8, zext.w and orc.b) that
changed due to gorci, grevi and pack not being part of Zb[abcs].
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Acked-by: Bin Meng <bmeng.cn@gmail.com >
Message-id: 20210911140016.834071-11-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-10-07 08:33:21 +10:00
fd4b81a304
target/riscv: Add instructions of the Zbc-extension
...
The following instructions are part of Zbc:
- clmul
- clmulh
- clmulr
Note that these instructions were already defined in the pre-0.93 and
the 0.93 draft-B proposals, but had not been omitted in the earlier
addition of draft-B to QEmu.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20210911140016.834071-10-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-10-07 08:33:16 +10:00
f36a4a89aa
target/riscv: Reassign instructions to the Zbs-extension
...
The following instructions are part of Zbs:
- b{set,clr,ext,inv}
- b{set,clr,ext,inv}i
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Acked-by: Bin Meng <bmeng.cn@gmail.com >
Message-id: 20210911140016.834071-9-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-10-07 08:33:13 +10:00
628d8c88c1
target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B)
...
The Zb[abcs] ratification package does not include the proposed
shift-one instructions. There currently is no clear plan to whether
these (or variants of them) will be ratified as Zbo (or a different
extension) or what the timeframe for such a decision could be.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Acked-by: Bin Meng <bmeng.cn@gmail.com >
Message-id: 20210911140016.834071-8-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-10-07 08:33:09 +10:00
dd98a74034
target/riscv: Remove the W-form instructions from Zbs
...
Zbs 1.0.0 (just as the 0.93 draft-B before) does not provide for W-form
instructions for Zbs (single-bit instructions). Remove them.
Note that these instructions had already been removed for the 0.93
version of the draft-B extention and have not been present in the
binutils patches circulating in January 2021.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Acked-by: Bin Meng <bmeng.cn@gmail.com >
Message-id: 20210911140016.834071-7-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-10-07 08:33:05 +10:00
bb4dc158e0
target/riscv: Reassign instructions to the Zba-extension
...
The following instructions are part of Zba:
- add.uw (RV64 only)
- sh[123]add (RV32 and RV64)
- sh[123]add.uw (RV64-only)
- slli.uw (RV64-only)
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Acked-by: Bin Meng <bmeng.cn@gmail.com >
Message-id: 20210911140016.834071-6-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-10-07 08:33:01 +10:00
45d1749c1c
target/riscv: clwz must ignore high bits (use shift-left & changed logic)
...
Assume clzw being executed on a register that is not sign-extended, such
as for the following sequence that uses (1ULL << 63) | 392 as the operand
to clzw:
bseti a2, zero, 63
addi a2, a2, 392
clzw a3, a2
The correct result of clzw would be 23, but the current implementation
returns -32 (as it performs a 64bit clz, which results in 0 leading zero
bits, and then subtracts 32).
Fix this by changing the implementation to:
1. shift the original register up by 32
2. performs a target-length (64bit) clz
3. return 32 if no bits are set
Marking this instruction as 'w-form' (i.e., setting ctx->w) would not
correctly model the behaviour, as the instruction should not perform
a zero-extensions on the input (after all, it is not a .uw instruction)
and the result is always in the range 0..32 (so neither a sign-extension
nor a zero-extension on the result will ever be needed). Consequently,
we do not set ctx->w and mark the instruction as EXT_NONE.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu >
Reviewed-by: LIU Zhiwei<zhiwei_liu@c-sky.com >
Message-id: 20210911140016.834071-4-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-10-07 08:32:47 +10:00
e47fb6c1e9
target/riscv: fix clzw implementation to operate on arg1
...
The refactored gen_clzw() uses ret as its argument, instead of arg1.
Fix it.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20210911140016.834071-3-philipp.tomsich@vrull.eu
Fixes: 6090391505alistair.francis@wdc.com >
2021-10-07 08:32:39 +10:00
c5b4ee5bb7
target/riscv: Introduce temporary in gen_add_uw()
...
Following the recent changes in translate.c, gen_add_uw() causes
failures on CF3 and SPEC2017 due to the reuse of arg1. Fix these
regressions by introducing a temporary.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20210911140016.834071-2-philipp.tomsich@vrull.eu
Fixes: 191d1dafaealistair.francis@wdc.com >
2021-10-07 08:32:21 +10:00
6922eee6ac
target/riscv: Use gen_shift_imm_fn for slli_uw
...
Always use tcg_gen_deposit_z_tl; the special case for
shamt >= 32 is handled there.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20210823195529.560295-21-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-09-01 11:59:12 +10:00
89c883091f
target/riscv: Use DisasExtend in shift operations
...
These operations are greatly simplified by ctx->w, which allows
us to fold gen_shiftw into gen_shift. Split gen_shifti into
gen_shift_imm_{fn,tl} like we do for gen_arith_imm_{fn,tl}.
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20210823195529.560295-13-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-09-01 11:59:12 +10:00
6090391505
target/riscv: Add DisasExtend to gen_unary
...
Use ctx->w for ctpopw, which is the only one that can
re-use the generic algorithm for the narrow operation.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20210823195529.560295-12-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-09-01 11:59:12 +10:00
f84ed8c2df
target/riscv: Move gen_* helpers for RVB
...
Move these helpers near their use by the trans_*
functions within insn_trans/trans_rvb.c.inc.
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20210823195529.560295-11-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-09-01 11:59:12 +10:00
191d1dafae
target/riscv: Add DisasExtend to gen_arith*
...
Most arithmetic does not require extending the inputs.
Exceptions include division, comparison and minmax.
Begin using ctx->w, which allows elimination of gen_addw,
gen_subw, gen_mulw.
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20210823195529.560295-7-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-09-01 11:59:12 +10:00
867c81968a
target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr
...
We will require the context to handle RV64 word operations.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20210823195529.560295-5-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-09-01 11:59:12 +10:00
3a4a43e4e2
target/riscv: rvb: add/shift with prefix zero-extend
...
Signed-off-by: Kito Cheng <kito.cheng@sifive.com >
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20210505160620.15723-16-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-06-08 09:59:45 +10:00
920a1f9955
target/riscv: rvb: address calculation
...
Signed-off-by: Kito Cheng <kito.cheng@sifive.com >
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20210505160620.15723-15-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-06-08 09:59:45 +10:00
c24f0422fb
target/riscv: rvb: generalized or-combine
...
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20210505160620.15723-14-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-06-08 09:59:45 +10:00
831ec7f3d1
target/riscv: rvb: generalized reverse
...
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20210505160620.15723-13-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-06-08 09:59:45 +10:00
e58529a8d0
target/riscv: rvb: rotate (left/right)
...
Signed-off-by: Kito Cheng <kito.cheng@sifive.com >
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20210505160620.15723-12-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-06-08 09:59:45 +10:00
91d8fc6768
target/riscv: rvb: shift ones
...
Signed-off-by: Kito Cheng <kito.cheng@sifive.com >
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20210505160620.15723-11-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-06-08 09:59:45 +10:00
23cd17773b
target/riscv: rvb: single-bit instructions
...
Signed-off-by: Kito Cheng <kito.cheng@sifive.com >
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20210505160620.15723-10-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-06-08 09:59:45 +10:00
2a81973829
target/riscv: rvb: sign-extend instructions
...
Signed-off-by: Kito Cheng <kito.cheng@sifive.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Message-id: 20210505160620.15723-8-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-06-08 09:59:44 +10:00
82655d8115
target/riscv: rvb: min/max instructions
...
Signed-off-by: Kito Cheng <kito.cheng@sifive.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Message-id: 20210505160620.15723-7-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-06-08 09:59:44 +10:00
6ef5843182
target/riscv: rvb: pack two words into one register
...
Signed-off-by: Kito Cheng <kito.cheng@sifive.com >
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20210505160620.15723-6-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-06-08 09:59:44 +10:00
0bcdb686e5
target/riscv: rvb: logic-with-negate
...
Signed-off-by: Kito Cheng <kito.cheng@sifive.com >
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20210505160620.15723-5-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-06-08 09:59:44 +10:00
1e16310ca1
target/riscv: rvb: count bits set
...
Signed-off-by: Kito Cheng <kito.cheng@sifive.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Message-id: 20210505160620.15723-4-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-06-08 09:59:44 +10:00
438240185a
target/riscv: rvb: count leading/trailing zeros
...
Signed-off-by: Kito Cheng <kito.cheng@sifive.com >
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20210505160620.15723-3-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-06-08 09:59:43 +10:00
