bb5de52524
target: Widen pc/cs_base in cpu_get_tb_cpu_state
...
Signed-off-by: Anton Johansson <anjo@rev.ng >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20230621135633.1649-4-anjo@rev.ng >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2023-06-26 17:32:59 +02:00
b83e4f1db4
target/riscv: Fix initialized value for cur_pmmask
...
We initialize cur_pmmask as -1(UINT32_MAX/UINT64_MAX) and regard it
as if pointer mask is disabled in current implementation. However,
the addresses for vector load/store will be adjusted to zero in this
case and -1(UINT32_MAX/UINT64_MAX) is valid value for pmmask when
pointer mask is enabled.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn >
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn >
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com >
Message-Id: <20230610094651.43786-1-liweiwei@iscas.ac.cn >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-06-13 17:42:50 +10:00
e0b343b5fa
target/riscv: Reuse tb->flags.FS
...
When misa.F is 0 tb->flags.FS field is unused and can be used to save
the current state of smstateen0.FCSR check which is needed by the
floating point translation routines.
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn >
Message-Id: <20230518175058.2772506-3-mchitale@ventanamicro.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-06-13 17:24:00 +10:00
e9c39713ea
target/riscv: Change the return type of pmp_hart_has_privs() to bool
...
We no longer need the pmp_index for matched PMP entry now.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn >
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20230517091519.34439-5-liweiwei@iscas.ac.cn >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-06-13 17:09:13 +10:00
bfc7ee1224
target/riscv: Move pmp_get_tlb_size apart from get_physical_address_pmp
...
pmp_get_tlb_size can be separated from get_physical_address_pmp and is only
needed when ret == TRANSLATE_SUCCESS.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn >
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn >
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20230517091519.34439-3-liweiwei@iscas.ac.cn >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-06-13 17:07:28 +10:00
dc7b599332
target/riscv: Update pmp_get_tlb_size()
...
PMP entries before (including) the matched PMP entry may only cover partial
of the TLB page, and this may split the page into regions with different
permissions. Such as for PMP0 (0x80000008~0x8000000F, R) and PMP1 (0x80000000~
0x80000FFF, RWX), write access to 0x80000000 will match PMP1. However we cannot
cache the translation result in the TLB since this will make the write access
to 0x80000008 bypass the check of PMP0. So we should check all of them instead
of the matched PMP entry in pmp_get_tlb_size() and set the tlb_size to 1 in
this case.
Set tlb_size to TARGET_PAGE_SIZE if PMP is not support or there is no PMP rules.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn >
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn >
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20230517091519.34439-2-liweiwei@iscas.ac.cn >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-06-13 17:06:39 +10:00
70f168f88c
tcg: Split out tcg/oversized-guest.h
...
Move a use of TARGET_LONG_BITS out of tcg/tcg.h.
Include the new file only where required.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2023-06-05 12:04:28 -07:00
190e9f8ec1
riscv: Make sure an exception is raised if a pte is malformed
...
As per the specification, in 64-bit, if any of the pte reserved bits
60-54 is set an exception should be triggered (see 4.4.1, "Addressing and
Memory Protection"). In addition, we must check the napot/pbmt bits are
not set if those extensions are not active.
Reported-by: Andrea Parri <andrea@rivosinc.com >
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20230420150220.60919-1-alexghiti@rivosinc.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-05-05 10:49:50 +10:00
7bf14a2f37
target/riscv: Fix Guest Physical Address Translation
...
Before changing the flow check for sv39/48/57.
According to specification (for Supervisor mode):
Sv39 implementations support a 39-bit virtual address space, divided into 4 KiB
pages.
Instruction fetch addresses and load and store effective addresses, which are
64 bits,
must have bits 63–39 all equal to bit 38, or else a page-fault exception will
occur.
Likewise for Sv48 and Sv57.
So the high bits are equal to bit 38 for sv39.
According to specification (for Hypervisor mode):
For Sv39x4, address bits of the guest physical address 63:41 must all be zeros,
or else a
guest-page-fault exception occurs.
Likewise for Sv48x4 and Sv57x4.
For Sv48x4 address bits 63:50 must all be zeros, or else a guest-page-fault
exception occurs.
For Sv57x4 address bits 63:59 must all be zeros, or else a guest-page-fault
exception occurs.
For example we are trying to access address 0xffff_ffff_ff01_0000 with only
G-translation enabled.
So expected behavior is to generate exception. But qemu doesn't generate such
exception.
For the old check, we get
va_bits == 41, mask == (1 << 24) - 1, masked_msbs == (0xffff_ffff_ff01_0000 >>
40) & mask == mask.
Accordingly, the condition masked_msbs != 0 && masked_msbs != mask is not
fulfilled
and the check passes.
Signed-off-by: Irina Ryapolova <irina.ryapolova@syntacore.com >
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20230418075423.26217-1-irina.ryapolova@syntacore.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-05-05 10:49:50 +10:00
38303e8a2c
target/riscv: Reorg sum check in get_physical_address
...
Implement this by adjusting prot, which reduces the set of
checks required. This prevents exec to be set for U pages
in MMUIdx_S_SUM. While it had been technically incorrect,
it did not manifest as a bug, because we will never attempt
to execute from MMUIdx_S_SUM.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn >
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com >
Message-Id: <20230325105429.1142530-26-richard.henderson@linaro.org >
Message-Id: <20230412114333.118895-26-richard.henderson@linaro.org >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-05-05 10:49:50 +10:00
e1dd15076b
target/riscv: Reorg access check in get_physical_address
...
We were effectively computing the protection bits twice,
once while performing access checks and once while returning
the valid bits to the caller. Reorg so we do this once.
Move the computation of mxr close to its single use.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn >
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com >
Message-Id: <20230325105429.1142530-25-richard.henderson@linaro.org >
Message-Id: <20230412114333.118895-25-richard.henderson@linaro.org >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-05-05 10:49:50 +10:00
a9d2e3ed4d
target/riscv: Merge checks for reserved pte flags
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn >
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com >
Message-Id: <20230325105429.1142530-24-richard.henderson@linaro.org >
Message-Id: <20230412114333.118895-24-richard.henderson@linaro.org >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-05-05 10:49:50 +10:00
356c8331d6
target/riscv: Don't modify SUM with is_debug
...
If we want to give the debugger a greater view of memory than
the cpu, we should simply disable the access check entirely,
not simply for this one corner case.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn >
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com >
Message-Id: <20230325105429.1142530-23-richard.henderson@linaro.org >
Message-Id: <20230412114333.118895-23-richard.henderson@linaro.org >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-05-05 10:49:50 +10:00
0a19bf5e37
target/riscv: Suppress pte update with is_debug
...
The debugger should not modify PTE_A or PTE_D.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn >
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com >
Message-Id: <20230325105429.1142530-22-richard.henderson@linaro.org >
Message-Id: <20230412114333.118895-22-richard.henderson@linaro.org >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-05-05 10:49:50 +10:00
59688aa023
target/riscv: Move leaf pte processing out of level loop
...
Move the code that never loops outside of the loop.
Unchain the if-return-else statements.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn >
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com >
Message-Id: <20230325105429.1142530-21-richard.henderson@linaro.org >
Message-Id: <20230412114333.118895-21-richard.henderson@linaro.org >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-05-05 10:49:50 +10:00
8d6a00cdc0
target/riscv: Hoist pbmte and hade out of the level loop
...
These values are constant for every level of pte lookup.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn >
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com >
Message-Id: <20230325105429.1142530-20-richard.henderson@linaro.org >
Message-Id: <20230412114333.118895-20-richard.henderson@linaro.org >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-05-05 10:49:50 +10:00
a427c83633
target/riscv: Hoist second stage mode change to callers
...
Move the check from the top of get_physical_address to
the two callers, where passing mmu_idx makes no sense.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn >
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com >
Message-Id: <20230325105429.1142530-19-richard.henderson@linaro.org >
Message-Id: <20230412114333.118895-19-richard.henderson@linaro.org >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-05-05 10:49:50 +10:00
eaecd473ca
target/riscv: Check SUM in the correct register
...
Table 9.5 "Effect of MPRV..." specifies that MPV=1 uses VS-level
vsstatus.SUM instead of HS-level sstatus.SUM.
For HLV/HSV instructions, the HS-level register does not apply, but
the VS-level register presumably does, though this is not mentioned
explicitly in the manual. However, it matches the behavior for MPV.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn >
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com >
Message-Id: <20230325105429.1142530-18-richard.henderson@linaro.org >
Message-Id: <20230412114333.118895-18-richard.henderson@linaro.org >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-05-05 10:49:50 +10:00
696bacde95
target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_index
...
Incorporate the virt_enabled and MPV checks into the cpu_mmu_index
function, so we don't have to keep doing it within tlb_fill and
subroutines. This also elides a flush on changes to MPV.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn >
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com >
Message-Id: <20230325105429.1142530-17-richard.henderson@linaro.org >
Message-Id: <20230412114333.118895-17-richard.henderson@linaro.org >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-05-05 10:49:50 +10:00
9de7b7b5c7
target/riscv: Move hstatus.spvp check to check_access_hlsv
...
The current cpu_mmu_index value is really irrelevant to
the HLV/HSV lookup. Provide the correct priv level directly.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn >
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com >
Message-Id: <20230325105429.1142530-16-richard.henderson@linaro.org >
Message-Id: <20230412114333.118895-16-richard.henderson@linaro.org >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-05-05 10:49:50 +10:00
02369f7906
target/riscv: Introduce mmuidx_2stage
...
Move and rename riscv_cpu_two_stage_lookup, to match
the other mmuidx_* functions.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn >
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com >
Message-Id: <20230325105429.1142530-15-richard.henderson@linaro.org >
Message-Id: <20230412114333.118895-15-richard.henderson@linaro.org >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-05-05 10:49:50 +10:00
340b5805db
target/riscv: Introduce mmuidx_priv
...
Use the priv level encoded into the mmu_idx, rather than
starting from env->priv. We have already checked MPRV+MPP
in riscv_cpu_mmu_index -- no need to repeat that.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn >
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com >
Message-Id: <20230325105429.1142530-14-richard.henderson@linaro.org >
Message-Id: <20230412114333.118895-14-richard.henderson@linaro.org >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-05-05 10:49:50 +10:00
4005a799f1
target/riscv: Introduce mmuidx_sum
...
In get_physical_address, we should use the setting passed
via mmu_idx rather than checking env->mstatus directly.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn >
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com >
Message-Id: <20230325105429.1142530-13-richard.henderson@linaro.org >
Message-Id: <20230412114333.118895-13-richard.henderson@linaro.org >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-05-05 10:49:50 +10:00
3df44173e9
target/riscv: Rename MMU_HYP_ACCESS_BIT to MMU_2STAGE_BIT
...
We will enable more uses of this bit in the future.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn >
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com >
Message-Id: <20230325105429.1142530-12-richard.henderson@linaro.org >
Message-Id: <20230412114333.118895-12-richard.henderson@linaro.org >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-05-05 10:49:50 +10:00
0f58cbbeea
target/riscv: Handle HLV, HSV via helpers
...
Implement these instructions via helpers, in expectation
of determining the mmu_idx to use at runtime. This allows
the permission check to also be moved out of line, which
allows HLSX to be removed from TB_FLAGS.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn >
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com >
Message-Id: <20230325105429.1142530-11-richard.henderson@linaro.org >
Message-Id: <20230412114333.118895-11-richard.henderson@linaro.org >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-05-05 10:49:50 +10:00
c8f8a9957e
target/riscv: Reduce overhead of MSTATUS_SUM change
...
Kernel needs to access user mode memory e.g. during syscalls, the window
is usually opened up for a very limited time through MSTATUS.SUM, the
overhead is too much if tlb_flush() gets called for every SUM change.
This patch creates a separate MMU index for S+SUM, so that it's not
necessary to flush tlb anymore when SUM changes. This is similar to how
ARM handles Privileged Access Never (PAN).
Result of 'pipe 10' from unixbench boosts from 223656 to 1705006. Many
other syscalls benefit a lot from this too.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: Fei Wu <fei2.wu@intel.com >
Message-Id: <20230324054154.414846-3-fei2.wu@intel.com >
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn >
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com >
Message-Id: <20230325105429.1142530-8-richard.henderson@linaro.org >
Message-Id: <20230412114333.118895-8-richard.henderson@linaro.org >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-05-05 10:49:50 +10:00
47debc7280
target/riscv: Separate priv from mmu_idx
...
Currently it's assumed the 2 low bits of mmu_idx map to privilege mode,
this assumption won't last as we are about to add more mmu_idx. Here an
individual priv field is added into TB_FLAGS.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: Fei Wu <fei2.wu@intel.com >
Message-Id: <20230324054154.414846-2-fei2.wu@intel.com >
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn >
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com >
Message-Id: <20230325105429.1142530-7-richard.henderson@linaro.org >
Message-Id: <20230412114333.118895-7-richard.henderson@linaro.org >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-05-05 10:49:50 +10:00
4acaa133b1
target/riscv: Add a tb flags field for vstart
...
Once we mistook the vstart directly from the env->vstart. As env->vstart is not
a constant, we should record it in the tb flags if we want to use
it in translation.
Reported-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com >
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn >
Message-Id: <20230324143031.1093-5-zhiwei_liu@linux.alibaba.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com >
Message-Id: <20230325105429.1142530-6-richard.henderson@linaro.org >
Message-Id: <20230412114333.118895-6-richard.henderson@linaro.org >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-05-05 10:49:50 +10:00
25f3ddff5f
target/riscv: Remove mstatus_hs_{fs, vs} from tb_flags
...
Merge with mstatus_{fs,vs}. We might perform a redundant
assignment to one or the other field, but it's a trivial
and saves 4 bits from TB_FLAGS.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn >
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com >
Message-Id: <20230325105429.1142530-5-richard.henderson@linaro.org >
Message-Id: <20230412114333.118895-5-richard.henderson@linaro.org >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-05-05 10:49:50 +10:00
ebd476488d
target/riscv: Encode the FS and VS on a normal way for tb flags
...
Reuse the MSTATUS_FS and MSTATUS_VS for the tb flags positions is not a
normal way.
It will make it hard to change the tb flags layout. And even worse, if we
want to keep tb flags for a same extension togather without a hole.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com >
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn >
Message-Id: <20230324143031.1093-4-zhiwei_liu@linux.alibaba.com >
[rth: Adjust trans_rvf.c.inc as well; use the typedef]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com >
Message-Id: <20230325105429.1142530-4-richard.henderson@linaro.org >
Message-Id: <20230412114333.118895-4-richard.henderson@linaro.org >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-05-05 10:49:50 +10:00
f196639024
target/riscv: Extract virt enabled state from tb flags
...
Virt enabled state is not a constant, so we should put it into tb flags.
Thus we can use it like a constant condition at translation phase.
Reported-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com >
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn >
Message-Id: <20230324143031.1093-2-zhiwei_liu@linux.alibaba.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com >
Message-Id: <20230325105429.1142530-2-richard.henderson@linaro.org >
Message-Id: <20230412114333.118895-2-richard.henderson@linaro.org >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-05-05 10:49:50 +10:00
0c98ccef49
target/riscv: Legalize MPP value in write_mstatus
...
mstatus.MPP field is a WARL field since priv version 1.11, so we
remain it unchanged if an invalid value is written into it. And
after this, RVH shouldn't be passed to riscv_cpu_set_mode().
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn >
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20230407014743.18779-4-liweiwei@iscas.ac.cn >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-05-05 10:49:50 +10:00
44b8f74b00
target/riscv: Use PRV_RESERVED instead of PRV_H
...
PRV_H has no real meaning, but just a reserved privilege mode currently.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn >
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20230407014743.18779-3-liweiwei@iscas.ac.cn >
[ Changes by AF:
- Convert one missing use of PRV_H
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-05-05 10:49:50 +10:00
246f87960a
target/riscv: Fix lines with over 80 characters
...
Fix lines with over 80 characters for both code and comments.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn >
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn >
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com >
Acked-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com >
Message-Id: <20230405085813.40643-5-liweiwei@iscas.ac.cn >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-05-05 10:49:50 +10:00
3b57254d8a
target/riscv: Fix format for comments
...
Fix formats for multi-lines comments.
Add spaces around single line comments(after "/*" and before "*/").
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn >
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn >
Acked-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com >
Message-Id: <20230405085813.40643-4-liweiwei@iscas.ac.cn >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-05-05 10:49:50 +10:00
c45eff30cb
target/riscv: Fix format for indentation
...
Fix identation problems, and try to use the same indentation strategy
in the same file.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn >
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn >
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com >
Acked-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com >
Message-Id: <20230405085813.40643-3-liweiwei@iscas.ac.cn >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-05-05 10:49:50 +10:00
38256529f3
target/riscv: Remove riscv_cpu_virt_enabled()
...
Directly use env->virt_enabled instead.
Suggested-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com >
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn >
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com >
Message-Id: <20230405085813.40643-2-liweiwei@iscas.ac.cn >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-05-05 10:49:50 +10:00
77dff6509c
target/riscv: Fix addr type for get_physical_address
...
Function get_physical_address() translates both virtual address and
guest physical address, and the latter is 34-bits for Sv32x4. So we
should use vaddr type for 'addr' parameter.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn >
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20230329101928.83856-1-liweiwei@iscas.ac.cn >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-05-05 10:49:50 +10:00
628f0ec1ed
target/riscv: Remove redundant parentheses
...
Remove redundant parentheses in get_physical_address.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn >
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20230327080858.39703-8-liweiwei@iscas.ac.cn >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-05-05 10:49:50 +10:00
b3c5077bef
target/riscv: Convert env->virt to a bool env->virt_enabled
...
Currently we only use the env->virt to encode the virtual mode enabled
status. Let's make it a bool type.
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com >
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn >
Message-ID: <20230325145348.1208-1-zhiwei_liu@linux.alibaba.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20230327080858.39703-6-liweiwei@iscas.ac.cn >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-05-05 10:49:50 +10:00
c43732f505
target/riscv: Remove check on RVH for riscv_cpu_set_virt_enabled
...
In current implementation, riscv_cpu_set_virt_enabled is only called when
RVH is enabled.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn >
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20230327080858.39703-5-liweiwei@iscas.ac.cn >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-05-05 10:49:50 +10:00
286629216c
target/riscv: Remove check on RVH for riscv_cpu_virt_enabled
...
Since env->virt.VIRT_ONOFF is initialized as false, and will not be set
to true when RVH is disabled, so we can just return this bit(false) when
RVH is not disabled.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn >
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20230327080858.39703-4-liweiwei@iscas.ac.cn >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-05-05 10:49:50 +10:00
2136b6c30c
target/riscv: Remove redundant call to riscv_cpu_virt_enabled
...
The assignment is done under the condition riscv_cpu_virt_enabled()=true.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn >
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20230327080858.39703-2-liweiwei@iscas.ac.cn >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-05-05 10:49:50 +10:00
bbb9fc2591
target/riscv: Simplify type conversion for CPURISCVState
...
Use CPURISCVState as argument directly in riscv_cpu_update_mip and
riscv_timer_write_timecmp, since type converts from CPURISCVState to
RISCVCPU in many caller of them and then back to CPURISCVState in them.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn >
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com >
Message-Id: <20230309071329.45932-4-liweiwei@iscas.ac.cn >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-05-05 10:49:49 +10:00
9c33e08b2b
target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig
...
Use riscv_cpu_cfg(env) instead of env_archcpu().cfg.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn >
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com >
Message-Id: <20230309071329.45932-2-liweiwei@iscas.ac.cn >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-05-05 10:49:49 +10:00
8e5aded3de
Merge patch series "target/riscv: Add support for Svadu extension"
...
Weiwei Li <liweiwei@iscas.ac.cn > says:
This patchset adds support svadu extension. It also fixes some
relationship between *envcfg fields and Svpbmt/Sstc extensions.
Specification for Svadu extension can be found in:
https://github.com/riscv/riscv-svadu
* b4-shazam-merge:
target/riscv: Export Svadu property
target/riscv: Add *envcfg.HADE related check in address translation
target/riscv: Add *envcfg.PBMTE related check in address translation
target/riscv: Add csr support for svadu
target/riscv: Fix the relationship of PBMTE/STCE fields between menvcfg and henvcfg
target/riscv: Fix the relationship between menvcfg.PBMTE/STCE and Svpbmt/Sstc extensions
Message-ID: <20230224040852.37109-1-liweiwei@iscas.ac.cn >
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com >
2023-03-01 17:30:34 -08:00
0af3f115e6
target/riscv: Add *envcfg.HADE related check in address translation
...
When menvcfg.HADE is 1, hardware updating of PTE A/D bits is enabled
during single-stage address translation. When the hypervisor extension is
implemented, if menvcfg.HADE is 1, hardware updating of PTE A/D bits is
enabled during G-stage address translation.
Set *envcfg.HADE default true for backward compatibility.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn >
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn >
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com >
Message-ID: <20230224040852.37109-6-liweiwei@iscas.ac.cn >
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com >
2023-03-01 17:28:17 -08:00
7a6613da99
target/riscv: Add *envcfg.PBMTE related check in address translation
...
menvcfg.PBMTE bit controls whether the Svpbmt extension is available
for use in S-mode and G-stage address translation.
henvcfg.PBMTE bit controls whether the Svpbmt extension is available
for use in VS-stage address translation.
Set *envcfg.PBMTE default true for backward compatibility.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn >
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn >
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com >
Message-ID: <20230224040852.37109-5-liweiwei@iscas.ac.cn >
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com >
2023-03-01 17:28:16 -08:00
312f632f4c
Merge patch series "target/riscv: Some updates to float point related extensions"
...
RISC-V defines a handful of extensions related to floating point, along
with various relationships between these and other extensions. This
patch set adds support for the Zvfh, Zvhfmin, and Zve64d extensions;
along with a handful of fixes and cleanups related to the other
floating-point extension relationships.
* b4-shazam-merge
target/riscv: Expose properties for Zv* extensions
target/riscv: Simplify check for EEW = 64 in trans_rvv.c.inc
target/riscv: Fix check for vector load/store instructions when EEW=64
target/riscv: Add support for Zvfh/zvfhmin extensions
target/riscv: Remove rebundunt check for zve32f and zve64f
target/riscv: Replace check for F/D to Zve32f/Zve64d in trans_rvv.c.inc
target/riscv: Simplify check for Zve32f and Zve64f
target/riscv: Indent fixes in cpu.c
target/riscv: Add propertie check for Zvfh{min} extensions
target/riscv: Fix relationship between V, Zve*, F and D
target/riscv: Add cfg properties for Zv* extensions
target/riscv: Simplify the check for Zfhmin and Zhinxmin
target/riscv: Fix the relationship between Zhinxmin and Zhinx
target/riscv: Fix the relationship between Zfhmin and Zfh
Message-ID: <20230215020539.4788-1-liweiwei@iscas.ac.cn >
[Palmer: commit text]
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com >
2023-03-01 15:18:49 -08:00
3f4a5a5314
target/riscv: Simplify check for Zve32f and Zve64f
...
V/Zve64f depend on Zve32f, so we can only check Zve32f in these cases.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn >
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn >
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com >
Message-ID: <20230215020539.4788-9-liweiwei@iscas.ac.cn >
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com >
2023-03-01 15:17:51 -08:00
