190e9f8ec1
riscv: Make sure an exception is raised if a pte is malformed
...
As per the specification, in 64-bit, if any of the pte reserved bits
60-54 is set an exception should be triggered (see 4.4.1, "Addressing and
Memory Protection"). In addition, we must check the napot/pbmt bits are
not set if those extensions are not active.
Reported-by: Andrea Parri <andrea@rivosinc.com >
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20230420150220.60919-1-alexghiti@rivosinc.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-05-05 10:49:50 +10:00
42967f4073
target/riscv: Add a general status enum for extensions
...
The pointer masking is the only extension that directly use status.
The vector or float extension uses the status in an indirect way.
Replace the pointer masking extension special status fields with
the general status.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com >
Message-Id: <20230324143031.1093-3-zhiwei_liu@linux.alibaba.com >
[rth: Add a typedef for the enum]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn >
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com >
Message-Id: <20230325105429.1142530-3-richard.henderson@linaro.org >
Message-Id: <20230412114333.118895-3-richard.henderson@linaro.org >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-05-05 10:49:50 +10:00
44b8f74b00
target/riscv: Use PRV_RESERVED instead of PRV_H
...
PRV_H has no real meaning, but just a reserved privilege mode currently.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn >
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20230407014743.18779-3-liweiwei@iscas.ac.cn >
[ Changes by AF:
- Convert one missing use of PRV_H
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-05-05 10:49:50 +10:00
3b57254d8a
target/riscv: Fix format for comments
...
Fix formats for multi-lines comments.
Add spaces around single line comments(after "/*" and before "*/").
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn >
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn >
Acked-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com >
Message-Id: <20230405085813.40643-4-liweiwei@iscas.ac.cn >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-05-05 10:49:50 +10:00
b3c5077bef
target/riscv: Convert env->virt to a bool env->virt_enabled
...
Currently we only use the env->virt to encode the virtual mode enabled
status. Let's make it a bool type.
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com >
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn >
Message-ID: <20230325145348.1208-1-zhiwei_liu@linux.alibaba.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20230327080858.39703-6-liweiwei@iscas.ac.cn >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-05-05 10:49:50 +10:00
ce3af0bbbc
target/riscv: add support for Zcmt extension
...
Add encode, trans* functions and helper functions support for Zcmt
instrutions.
Add support for jvt csr.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn >
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20230307081403.61950-8-liweiwei@iscas.ac.cn >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-05-05 10:49:50 +10:00
0d190bd394
target/riscv: Add csr support for svadu
...
Add ext_svadu property
Add HADE field in *envcfg:
* menvcfg.HADE is read-only zero if Svadu is not implemented.
* henvcfg.HADE is read-only zero if menvcfg.HADE is zero.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn >
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn >
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com >
Message-ID: <20230224040852.37109-4-liweiwei@iscas.ac.cn >
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com >
2023-03-01 17:28:15 -08:00
3bee0e4010
target/riscv: Add smstateen support
...
Smstateen extension specifies a mechanism to close
the potential covert channels that could cause security issues.
This patch adds the CSRs defined in the specification and
the corresponding predicates and read/write functions.
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com >
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20221016124726.102129-2-mchitale@ventanamicro.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-01-06 10:42:55 +10:00
31b9798d82
target/riscv: debug: Introduce tinfo CSR
...
tinfo.info:
One bit for each possible type enumerated in tdata1.
If the bit is set, then that type is supported by the currently
selected trigger.
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Signed-off-by: Bin Meng <bmeng.cn@gmail.com >
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com >
Message-Id: <20220909134215.1843865-6-bmeng.cn@gmail.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-09-27 11:23:57 +10:00
513eb437ae
target/riscv: Remove sideleg and sedeleg
...
sideleg and sedeleg csrs are not part of riscv isa spec
anymore, these csrs were part of N extension which
is removed from the riscv isa specification.
These commits removed all traces of these csrs from
riscv spec (https://github.com/riscv/riscv-isa-manual ) -
commit f8d27f805b65 ("Remove or downgrade more references to N extension (#674 )")
commit b6cade07034d ("Remove N extension chapter for now")
Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com >
Reviewed-by: Andrew Jones <ajones@ventanamicro.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20220824145255.400040-1-rpathak@ventanamicro.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-09-27 07:04:38 +10:00
1466448345
target/riscv: Add sscofpmf extension support
...
The Sscofpmf ('Ss' for Privileged arch and Supervisor-level extensions,
and 'cofpmf' for Count OverFlow and Privilege Mode Filtering)
extension allows the perf to handle overflow interrupts and filtering
support. This patch provides a framework for programmable
counters to leverage the extension. As the extension doesn't have any
provision for the overflow bit for fixed counters, the fixed events
can also be monitoring using programmable counters. The underlying
counters for cycle and instruction counters are always running. Thus,
a separate timer device is programmed to handle the overflow.
Tested-by: Heiko Stuebner <heiko@sntech.de >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Atish Patra <atish.patra@wdc.com >
Signed-off-by: Atish Patra <atishp@rivosinc.com >
Message-Id: <20220824221701.41932-2-atishp@rivosinc.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-09-07 09:19:15 +02:00
3ec0fe18a3
target/riscv: Add vstimecmp support
...
vstimecmp CSR allows the guest OS or to program the next guest timer
interrupt directly. Thus, hypervisor no longer need to inject the
timer interrupt to the guest if vstimecmp is used. This was ratified
as a part of the Sstc extension.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Atish Patra <atishp@rivosinc.com >
Message-Id: <20220824221357.41070-4-atishp@rivosinc.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-09-07 09:19:15 +02:00
43888c2f18
target/riscv: Add stimecmp support
...
stimecmp allows the supervisor mode to update stimecmp CSR directly
to program the next timer interrupt. This CSR is part of the Sstc
extension which was ratified recently.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Atish Patra <atishp@rivosinc.com >
Message-Id: <20220824221357.41070-3-atishp@rivosinc.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-09-07 09:19:15 +02:00
435774992e
target/riscv: Update default priority table for local interrupts
...
The latest AIA draft v0.3.0 defines a relatively simpler scheme for
default priority assignments where:
1) local interrupts 24 to 31 and 48 to 63 are reserved for custom use
and have implementation specific default priority.
2) remaining local interrupts 0 to 23 and 32 to 47 have a recommended
(not mandatory) priority assignments.
We update the default priority table and hviprio mapping as-per above.
Signed-off-by: Anup Patel <apatel@ventanamicro.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20220616031543.953776-3-apatel@ventanamicro.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-07-03 10:03:20 +10:00
df01af337f
target/riscv: Remove CSRs that set/clear an IMSIC interrupt file bits
...
Based on architecture review committee feedback, the [m|s|vs]seteienum,
[m|s|vs]clreienum, [m|s|vs]seteipnum, and [m|s|vs]clreipnum CSRs are
removed in the latest AIA draft v0.3.0 specification.
(Refer, https://github.com/riscv/riscv-aia/releases/tag/0.3.0-draft.31 )
These CSRs were mostly for software convenience and software can always
use [m|s|vs]iselect and [m|s|vs]ireg CSRs to update the IMSIC interrupt
file bits.
We update the IMSIC CSR emulation as-per above to match the latest AIA
draft specification.
Signed-off-by: Anup Patel <apatel@ventanamicro.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20220616031543.953776-2-apatel@ventanamicro.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-07-03 10:03:20 +10:00
b1675eeb3e
target/riscv: Implement mcountinhibit CSR
...
As per the privilege specification v1.11, mcountinhibit allows to start/stop
a pmu counter selectively.
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Atish Patra <atish.patra@wdc.com >
Signed-off-by: Atish Patra <atishp@rivosinc.com >
Message-Id: <20220620231603.2547260-6-atishp@rivosinc.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-07-03 10:03:20 +10:00
77442380ec
target/riscv: rvk: add CSR support for Zkr
...
- add SEED CSR which must be accessed with a read-write instruction:
A read-only instruction such as CSRRS/CSRRC with rs1=x0 or CSRRSI/CSRRCI
with uimm=0 will raise an illegal instruction exception.
- add USEED, SSEED fields for MSECCFG CSR
Co-authored-by: Ruibo Lu <luruibo2000@163.com >
Co-authored-by: Zewen Ye <lustrew@foxmail.com >
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn >
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20220423023510.30794-13-liweiwei@iscas.ac.cn >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-04-29 10:47:45 +10:00
29a9ec9bd8
target/riscv: Add *envcfg* CSRs support
...
The RISC-V privileged specification v1.12 defines few execution
environment configuration CSRs that can be used enable/disable
extensions per privilege levels.
Add the basic support for these CSRs.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Atish Patra <atishp@rivosinc.com >
Message-Id: <20220303185440.512391-6-atishp@rivosinc.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-04-22 10:35:16 +10:00
3e6a417c8a
target/riscv: Add support for mconfigptr
...
RISC-V privileged specification v1.12 introduced a mconfigptr
which will hold the physical address of a configuration data
structure. As Qemu doesn't have a configuration data structure,
is read as zero which is valid as per the priv spec.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Atish Patra <atishp@rivosinc.com >
Message-Id: <20220303185440.512391-5-atishp@rivosinc.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-04-22 10:35:16 +10:00
bbce8ba8e6
target/riscv: add support for svpbmt extension
...
- add PTE_PBMT bits: It uses two PTE bits, but otherwise has no effect on QEMU, since QEMU is sequentially consistent and doesn't model PMAs currently
- add PTE_PBMT bit check for inner PTE
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn >
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn >
Reviewed-by: Anup Patel <anup@brainfault.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20220204022658.18097-6-liweiwei@iscas.ac.cn >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-02-16 12:25:52 +10:00
2bacb22446
target/riscv: add support for svnapot extension
...
- add PTE_N bit
- add PTE_N bit check for inner PTE
- update address translation to support 64KiB continuous region (napot_bits = 4)
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn >
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn >
Reviewed-by: Anup Patel <anup@brainfault.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20220204022658.18097-4-liweiwei@iscas.ac.cn >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-02-16 12:25:52 +10:00
05e6ca5e15
target/riscv: Ignore reserved bits in PTE for RV64
...
Highest bits of PTE has been used for svpbmt, ref: [1], [2], so we
need to ignore them. They cannot be a part of ppn.
1: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture
4.4 Sv39: Page-Based 39-bit Virtual-Memory System
4.5 Sv48: Page-Based 48-bit Virtual-Memory System
2: https://github.com/riscv/virtual-memory/blob/main/specs/663-Svpbmt-diff.pdf
Signed-off-by: Guo Ren <ren_guo@c-sky.com >
Reviewed-by: Liu Zhiwei <zhiwei_liu@c-sky.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Cc: Bin Meng <bmeng.cn@gmail.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20220204022658.18097-2-liweiwei@iscas.ac.cn >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-02-16 12:25:52 +10:00
aa7508bbc6
target/riscv: Add defines for AIA CSRs
...
The RISC-V AIA specification extends RISC-V local interrupts and
introduces new CSRs. This patch adds defines for the new AIA CSRs.
Signed-off-by: Anup Patel <anup.patel@wdc.com >
Signed-off-by: Anup Patel <anup@brainfault.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Frank Chang <frank.chang@sifive.com >
Message-id: 20220204174700.534953-8-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-02-16 12:24:18 +10:00
cd032fe75c
target/riscv: Implement hgeie and hgeip CSRs
...
The hgeie and hgeip CSRs are required for emulating an external
interrupt controller capable of injecting virtual external interrupt
to Guest/VM running at VS-level.
Signed-off-by: Anup Patel <anup.patel@wdc.com >
Signed-off-by: Anup Patel <anup@brainfault.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Frank Chang <frank.chang@sifive.com >
Message-id: 20220204174700.534953-4-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-02-16 12:24:18 +10:00
881df35d3d
target/riscv: Implement SGEIP bit in hip and hie CSRs
...
A hypervisor can optionally take guest external interrupts using
SGEIP bit of hip and hie CSRs.
Signed-off-by: Anup Patel <anup.patel@wdc.com >
Signed-off-by: Anup Patel <anup@brainfault.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Frank Chang <frank.chang@sifive.com >
Message-id: 20220204174700.534953-3-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-02-16 12:24:18 +10:00
f310df58bd
target/riscv: Enable uxl field write
...
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20220120122050.41546-23-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-01-21 15:52:57 +10:00
457c360f9c
target/riscv: actual functions to realize crs 128-bit insns
...
The csrs are accessed through function pointers: we add 128-bit read
operations in the table for three csrs (writes fallback to the
64-bit version as the upper 64-bit information is handled elsewhere):
- misa, as mxl is needed for proper operation,
- mstatus and sstatus, to return sd
In addition, we also add read and write accesses to the machine and
supervisor scratch registers.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr >
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20220106210108.138226-19-frederic.petrot@univ-grenoble-alpes.fr
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-01-08 15:46:10 +10:00
2e56505475
target/riscv: rvv-1.0: add vlenb register
...
Signed-off-by: Greentime Hu <greentime.hu@sifive.com >
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20211210075704.23951-11-frank.chang@sifive.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-12-20 14:51:36 +10:00
4594fa5a96
target/riscv: rvv-1.0: add vcsr register
...
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com >
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20211210075704.23951-10-frank.chang@sifive.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-12-20 14:51:36 +10:00
89a81e376a
target/riscv: rvv-1.0: add sstatus VS field
...
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com >
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20211210075704.23951-6-frank.chang@sifive.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-12-20 14:51:36 +10:00
61b4b69d12
target/riscv: rvv-1.0: add mstatus VS field
...
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com >
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20211210075704.23951-4-frank.chang@sifive.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-12-20 14:51:36 +10:00
50d1608764
target/riscv: remove force HS exception
...
There is no need to "force an hs exception" as the current privilege
level, the state of the global ie and of the delegation registers should
be enough to route the interrupt to the appropriate privilege level in
riscv_cpu_do_interrupt. The is true for both asynchronous and
synchronous exceptions, specifically, guest page faults which must be
hardwired to zero hedeleg. As such the hs_force_except mechanism can be
removed.
Signed-off-by: Jose Martins <josemartins90@gmail.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20211026145126.11025-3-josemartins90@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-10-29 16:54:45 +10:00
138b5c5f8f
target/riscv: Add CSR defines for RISC-V PM extension
...
Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20211025173609.2724490-3-space.monkey.delivers@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-10-28 14:39:23 +10:00
99bc874fb3
target/riscv: Create RISCVMXL enumeration
...
Move the MXL_RV* defines to enumerators.
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20211020031709.359469-3-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-10-22 07:47:51 +10:00
31dbcff713
target/riscv: Remove some unused macros
...
Since commit 1a9540d1f1alistair.francis@wdc.com >
Reviewed-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Message-id: f4d8a7a035f39c0a35d44c1e371c5c99cc2fa15a.1634531504.git.alistair.francis@wdc.com
2021-10-22 07:47:51 +10:00
db70794ea8
target/riscv: csr: Rename HCOUNTEREN_CY and friends
...
The macro name HCOUNTEREN_CY suggests it is for CSR HCOUNTEREN, but
in fact it applies to M-mode and S-mode CSR too. Rename these macros
to have the COUNTEREN_ prefix.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20210915084601.24304-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-09-21 12:10:47 +10:00
a44da25aa6
target/riscv: Update the ePMP CSR address
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Update the ePMP CSRs to match the 0.9.3 ePMP spec
6145574723/Smepmp/Smepmp.pdfalistair.francis@wdc.com >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Message-id: 28c908de60b9b04fa20e63d113885c98586053f3.1630543194.git.alistair.francis@wdc.com
2021-09-21 07:56:49 +10:00
719f0f603c
target/riscv: fix wfi exception behavior
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The wfi exception trigger behavior should take into account user mode,
hstatus.vtw, and the fact the an wfi might raise different types of
exceptions depending on various factors:
If supervisor mode is not present:
- an illegal instruction exception should be generated if user mode
executes and wfi instruction and mstatus.tw = 1.
If supervisor mode is present:
- when a wfi instruction is executed, an illegal exception should be triggered
if either the current mode is user or the mode is supervisor and mstatus.tw is
set.
Plus, if the hypervisor extensions are enabled:
- a virtual instruction exception should be raised when a wfi is executed from
virtual-user or virtual-supervisor and hstatus.vtw is set.
Signed-off-by: Jose Martins <josemartins90@gmail.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20210420213656.85148-1-josemartins90@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-06-08 09:59:42 +10:00
e95ea34742
target/riscv: Remove the unused HSTATUS_WPRI macro
...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Message-id: e095b57af0d419c8ed822958f04dfc732d7beb7e.1619234854.git.alistair.francis@wdc.com
2021-05-11 20:02:07 +10:00
419ddf00ed
target/riscv: Remove the hardcoded SATP_MODE macro
...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 6b701769d6621f45ba1739334198e36a64fe04df.1619234854.git.alistair.francis@wdc.com
2021-05-11 20:02:07 +10:00
4fd7455bb3
target/riscv: Remove the hardcoded MSTATUS_SD macro
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: fcc125d96da941b56c817c9dd6068dc36478fc53.1619234854.git.alistair.francis@wdc.com
2021-05-11 20:02:07 +10:00
994b6bb2db
target/riscv: Remove the hardcoded HGATP_MODE macro
...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Message-id: 665f624bfdc2e3ca64265004b07de7489c77a766.1619234854.git.alistair.francis@wdc.com
2021-05-11 20:02:07 +10:00
5f10e6d895
target/riscv: Remove the hardcoded SSTATUS_SD macro
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This also ensures that the SD bit is not writable.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Message-id: 9ea842309f0fd7adff172790f5b5fc058b40f2f1.1619234854.git.alistair.francis@wdc.com
2021-05-11 20:02:07 +10:00
db9f1dac48
target/riscv: Define ePMP mseccfg
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Use address 0x390 and 0x391 for the ePMP CSRs.
Signed-off-by: Hongzheng-Li <Ethan.Lee.QNL@gmail.com >
Signed-off-by: Hou Weiying <weiying_hou@outlook.com >
Signed-off-by: Myriad-Dreamin <camiyoru@gmail.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Message-id: 63245b559f477a9ce6d4f930136d2d7fd7f99c78.1618812899.git.alistair.francis@wdc.com
[ Changes by AF:
- Tidy up commit message
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
2021-05-11 20:02:06 +10:00
330d2ae32a
target/riscv: Convert the RISC-V exceptions to an enum
...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: f191dcf08bf413a822e743a7c7f824d68879a527.1617290165.git.alistair.francis@wdc.com
2021-05-11 20:02:06 +10:00
ac12b60103
target/riscv: Remove privilege v1.9 specific CSR related code
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Qemu doesn't support RISC-V privilege specification v1.9. Remove the
remaining v1.9 specific references from the implementation.
Signed-off-by: Atish Patra <atish.patra@wdc.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20210319194534.2082397-2-atish.patra@wdc.com >
[Changes by AF:
- Rebase on latest patches
- Bump the vmstate_riscv_cpu version_id and minimum_version_id
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-05-11 20:01:10 +10:00
43a9658889
target-riscv: support QMP dump-guest-memory
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Add the support needed for creating prstatus elf notes. This allows
us to use QMP dump-guest-memory.
Now ELF notes of RISC-V only contain prstatus elf notes.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com >
Signed-off-by: Mingwang Li <limingwang@huawei.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Andrew Jones <drjones@redhat.com >
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com >
Message-id: 20210201124458.1248-2-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-03-04 09:43:29 -05:00
a10b9d93ec
riscv: Add semihosting support
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Adapt the arm semihosting support code for RISCV. This implementation
is based on the standard for RISC-V semihosting version 0.2 as
documented in
https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2
Signed-off-by: Keith Packard <keithp@keithp.com >
Signed-off-by: Alex Bennée <alex.bennee@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20210107170717.2098982-6-keithp@keithp.com >
Message-Id: <20210108224256.2321-17-alex.bennee@linaro.org >
2021-01-18 10:05:06 +00:00
8987cdc481
target/riscv: csr: Remove compile time XLEN checks
...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Bin Meng <bin.meng@windriver.com >
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com >
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com >
Tested-by: Bin Meng <bin.meng@windriver.com >
Message-id: 7371180970b7db310d3a1da21d03d33499c2beb0.1608142916.git.alistair.francis@wdc.com
2020-12-17 21:56:44 -08:00
529577457c
target/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSR
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The TW and TSR fields should be bits 21 and 22 and not 30/29.
This was found while comparing QEMU behaviour against the sail formal
model (https://github.com/rems-project/sail-riscv/ ).
Signed-off-by: Alex Richardson <Alexander.Richardson@cl.cam.ac.uk >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20201130170117.71281-1-Alexander.Richardson@cl.cam.ac.uk
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2020-12-17 21:56:43 -08:00
