eef82872be
target/riscv: rvk: add cfg properties for zbk* and zk*
...
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn >
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn >
Acked-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20220423023510.30794-2-liweiwei@iscas.ac.cn >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-04-29 10:47:45 +10:00
9951ba948a
target/riscv: Support configuarable marchid, mvendorid, mipid CSR values
...
Allow user to set core's marchid, mvendorid, mipid CSRs through
-cpu command line option.
The default values of marchid and mipid are built with QEMU's version
numbers.
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Jim Shu <jim.shu@sifive.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Message-Id: <20220422040436.2233-1-frank.chang@sifive.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-04-29 10:47:45 +10:00
1acdb3b013
target/riscv: cpu: Add a config option for native debug
...
Add a config option to enable support for native M-mode debug.
This is disabled by default and can be enabled with 'debug=true'.
Signed-off-by: Bin Meng <bin.meng@windriver.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20220421003324.1134983-3-bmeng.cn@gmail.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-04-22 10:35:16 +10:00
e2f01f3c2e
hw/intc: Make RISC-V ACLINT mtime MMIO register writable
...
RISC-V privilege spec defines that mtime is exposed as a memory-mapped
machine-mode read-write register. However, as QEMU uses host monotonic
timer as timer source, this makes mtime to be read-only in RISC-V
ACLINT.
This patch makes mtime to be writable by recording the time delta value
between the mtime value to be written and the timer value at the time
mtime is written. Time delta value is then added back whenever the timer
value is retrieved.
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Jim Shu <jim.shu@sifive.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20220420080901.14655-4-frank.chang@sifive.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-04-22 10:35:16 +10:00
95799e36c1
target/riscv: Add initial support for the Sdtrig extension
...
This adds initial support for the Sdtrig extension via the Trigger
Module, as defined in the RISC-V Debug Specification [1].
Only "Address / Data Match" trigger (type 2) is implemented as of now,
which is mainly used for hardware breakpoint and watchpoint. The number
of type 2 triggers implemented is 2, which is the number that we can
find in the SiFive U54/U74 cores.
[1] https://github.com/riscv/riscv-debug-spec/raw/master/riscv-debug-stable.pdf
Signed-off-by: Bin Meng <bin.meng@windriver.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20220315065529.62198-2-bmeng.cn@gmail.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-04-22 10:35:16 +10:00
33fe584f70
target/riscv: Allow software access to MIP SEIP
...
The RISC-V specification states that:
"Supervisor-level external interrupts are made pending based on the
logical-OR of the software-writable SEIP bit and the signal from the
external interrupt controller."
We currently only allow either the interrupt controller or software to
set the bit, which is incorrect.
This patch removes the miclaim mask when writing MIP to allow M-mode
software to inject interrupts, even with an interrupt controller.
We then also need to keep track of which source is setting MIP_SEIP. The
final value is a OR of both, so we add two bools and use that to keep
track of the current state. This way either source can change without
losing the correct value.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/904
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20220317061817.3856850-3-alistair.francis@opensource.wdc.com >
2022-04-22 10:35:16 +10:00
29a9ec9bd8
target/riscv: Add *envcfg* CSRs support
...
The RISC-V privileged specification v1.12 defines few execution
environment configuration CSRs that can be used enable/disable
extensions per privilege levels.
Add the basic support for these CSRs.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Atish Patra <atishp@rivosinc.com >
Message-Id: <20220303185440.512391-6-atishp@rivosinc.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-04-22 10:35:16 +10:00
a4b2fa4331
target/riscv: Introduce privilege version field in the CSR ops.
...
To allow/disallow the CSR access based on the privilege spec, a new field
in the csr_ops is introduced. It also adds the privileged specification
version (v1.12) for the CSRs introduced in the v1.12. This includes the
new ratified extensions such as Vector, Hypervisor and secconfig CSR.
However, it doesn't enforce the privilege version in this commit.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Atish Patra <atishp@rivosinc.com >
Message-Id: <20220303185440.512391-4-atishp@rivosinc.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-04-22 10:35:16 +10:00
3a4af26d7a
target/riscv: Add the privileged spec version 1.12.0
...
Add the definition for ratified privileged specification version v1.12
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Atish Patra <atishp@rivosinc.com >
Message-Id: <20220303185440.512391-3-atishp@rivosinc.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-04-22 10:35:16 +10:00
a46d410c5c
target/riscv: Define simpler privileged spec version numbering
...
Currently, the privileged specification version are defined in
a complex manner for no benefit.
Simplify it by changing it to a simple enum based on.
Suggested-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Atish Patra <atishp@rivosinc.com >
Message-Id: <20220303185440.512391-2-atishp@rivosinc.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-04-22 10:35:16 +10:00
8905770b27
compiler.h: replace QEMU_NORETURN with G_NORETURN
...
G_NORETURN was introduced in glib 2.68, fallback to G_GNUC_NORETURN in
glib-compat.
Note that this attribute must be placed before the function declaration
(bringing a bit of consistency in qemu codebase usage).
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com >
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com >
Reviewed-by: Warner Losh <imp@bsdimp.com >
Message-Id: <20220420132624.2439741-20-marcandre.lureau@redhat.com >
2022-04-21 17:03:51 +04:00
69242e7e7e
Move CPU softfloat unions to cpu-float.h
...
The types are no longer used in bswap.h since commit
f930224fffmarcandre.lureau@redhat.com >
Message-Id: <20220323155743.1585078-29-marcandre.lureau@redhat.com >
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com >
2022-04-06 14:31:43 +02:00
b36e239e08
target: Use ArchCPU as interface to target CPU
...
ArchCPU is our interface with target-specific code. Use it as
a forward-declared opaque pointer (abstract type), having its
structure defined by each target.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Message-Id: <20220214183144.27402-15-f4bug@amsat.org >
2022-03-06 22:23:09 +01:00
9295b1aa92
target: Introduce and use OBJECT_DECLARE_CPU_TYPE() macro
...
Replace the boilerplate code to declare CPU QOM types
and macros, and forward-declare the CPU instance type.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Message-Id: <20220214183144.27402-14-f4bug@amsat.org >
2022-03-06 22:23:09 +01:00
1ea4a06af0
target: Use CPUArchState as interface to target-specific CPU state
...
While CPUState is our interface with generic code, CPUArchState is
our interface with target-specific code. Use CPUArchState as an
abstract type, defined by each target.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Message-Id: <20220214183144.27402-13-f4bug@amsat.org >
2022-03-06 22:23:09 +01:00
89ffdcec27
target/riscv: add cfg properties for zfinx, zdinx and zhinx{min}
...
Co-authored-by: ardxwe <ardxwe@gmail.com >
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn >
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20220211043920.28981-2-liweiwei@iscas.ac.cn >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-03-03 13:14:50 +10:00
c5d77ddd8e
target/riscv: add support for svinval extension
...
- sinval.vma, hinval.vvma and hinval.gvma do the same as sfence.vma, hfence.vvma and hfence.gvma except extension check
- do nothing other than extension check for sfence.w.inval and sfence.inval.ir
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn >
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn >
Reviewed-by: Anup Patel <anup@brainfault.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20220204022658.18097-5-liweiwei@iscas.ac.cn >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-02-16 12:25:52 +10:00
05e6ca5e15
target/riscv: Ignore reserved bits in PTE for RV64
...
Highest bits of PTE has been used for svpbmt, ref: [1], [2], so we
need to ignore them. They cannot be a part of ppn.
1: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture
4.4 Sv39: Page-Based 39-bit Virtual-Memory System
4.5 Sv48: Page-Based 48-bit Virtual-Memory System
2: https://github.com/riscv/virtual-memory/blob/main/specs/663-Svpbmt-diff.pdf
Signed-off-by: Guo Ren <ren_guo@c-sky.com >
Reviewed-by: Liu Zhiwei <zhiwei_liu@c-sky.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Cc: Bin Meng <bmeng.cn@gmail.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20220204022658.18097-2-liweiwei@iscas.ac.cn >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-02-16 12:25:52 +10:00
91870b510a
target/riscv: Allow users to force enable AIA CSRs in HART
...
We add "x-aia" command-line option for RISC-V HART using which
allows users to force enable CPU AIA CSRs without changing the
interrupt controller available in RISC-V machine.
Signed-off-by: Anup Patel <anup.patel@wdc.com >
Signed-off-by: Anup Patel <anup@brainfault.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Frank Chang <frank.chang@sifive.com >
Message-id: 20220204174700.534953-18-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-02-16 12:24:19 +10:00
d1ceff405a
target/riscv: Implement AIA xiselect and xireg CSRs
...
The AIA specification defines [m|s|vs]iselect and [m|s|vs]ireg CSRs
which allow indirect access to interrupt priority arrays and per-HART
IMSIC registers. This patch implements AIA xiselect and xireg CSRs.
Signed-off-by: Anup Patel <anup.patel@wdc.com >
Signed-off-by: Anup Patel <anup@brainfault.org >
Reviewed-by: Frank Chang <frank.chang@sifive.com >
Message-id: 20220204174700.534953-15-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-02-16 12:24:19 +10:00
2b60239879
target/riscv: Implement AIA hvictl and hviprioX CSRs
...
The AIA hvictl and hviprioX CSRs allow hypervisor to control
interrupts visible at VS-level. This patch implements AIA hvictl
and hviprioX CSRs.
Signed-off-by: Anup Patel <anup.patel@wdc.com >
Signed-off-by: Anup Patel <anup@brainfault.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Frank Chang <frank.chang@sifive.com >
Message-id: 20220204174700.534953-12-anup@brainfault.org
[ Changes by AF:
- Fix possible unintilised variable error in rmw_sie()
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-02-16 12:24:19 +10:00
d028ac7512
target/riscv: Implement AIA CSRs for 64 local interrupts on RV32
...
The AIA specification adds new CSRs for RV32 so that RISC-V hart can
support 64 local interrupts on both RV32 and RV64.
Signed-off-by: Anup Patel <anup.patel@wdc.com >
Signed-off-by: Anup Patel <anup@brainfault.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Frank Chang <frank.chang@sifive.com >
Message-id: 20220204174700.534953-11-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-02-16 12:24:19 +10:00
43dc93af36
target/riscv: Implement AIA local interrupt priorities
...
The AIA spec defines programmable 8-bit priority for each local interrupt
at M-level, S-level and VS-level so we extend local interrupt processing
to consider AIA interrupt priorities. The AIA CSRs which help software
configure local interrupt priorities will be added by subsequent patches.
Signed-off-by: Anup Patel <anup.patel@wdc.com >
Signed-off-by: Anup Patel <anup@brainfault.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20220204174700.534953-10-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-02-16 12:24:19 +10:00
69077dd687
target/riscv: Allow AIA device emulation to set ireg rmw callback
...
The AIA device emulation (such as AIA IMSIC) should be able to set
(or provide) AIA ireg read-modify-write callback for each privilege
level of a RISC-V HART.
Signed-off-by: Anup Patel <anup.patel@wdc.com >
Signed-off-by: Anup Patel <anup@brainfault.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Frank Chang <frank.chang@sifive.com >
Message-id: 20220204174700.534953-9-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-02-16 12:24:18 +10:00
32b0ada038
target/riscv: Add AIA cpu feature
...
We define a CPU feature for AIA CSR support in RISC-V CPUs which
can be set by machine/device emulation. The RISC-V CSR emulation
will also check this feature for emulating AIA CSRs.
Signed-off-by: Anup Patel <anup.patel@wdc.com >
Signed-off-by: Anup Patel <anup@brainfault.org >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Frank Chang <frank.chang@sifive.com >
Message-id: 20220204174700.534953-7-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-02-16 12:24:18 +10:00
f87adf23fa
target/riscv: Allow setting CPU feature from machine/device emulation
...
The machine or device emulation should be able to force set certain
CPU features because:
1) We can have certain CPU features which are in-general optional
but implemented by RISC-V CPUs on the machine.
2) We can have devices which require a certain CPU feature. For example,
AIA IMSIC devices expect AIA CSRs implemented by RISC-V CPUs.
Signed-off-by: Anup Patel <anup.patel@wdc.com >
Signed-off-by: Anup Patel <anup@brainfault.org >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Frank Chang <frank.chang@sifive.com >
Message-id: 20220204174700.534953-6-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-02-16 12:24:18 +10:00
cd032fe75c
target/riscv: Implement hgeie and hgeip CSRs
...
The hgeie and hgeip CSRs are required for emulating an external
interrupt controller capable of injecting virtual external interrupt
to Guest/VM running at VS-level.
Signed-off-by: Anup Patel <anup.patel@wdc.com >
Signed-off-by: Anup Patel <anup@brainfault.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Frank Chang <frank.chang@sifive.com >
Message-id: 20220204174700.534953-4-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-02-16 12:24:18 +10:00
0d429bd243
target/riscv: Add XVentanaCondOps custom extension
...
This adds the decoder and translation for the XVentanaCondOps custom
extension (vendor-defined by Ventana Micro Systems), which is
documented at https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf
This commit then also adds a guard-function (has_XVentanaCondOps_p)
and the decoder function to the table of decoders, enabling the
support for the XVentanaCondOps extension.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20220202005249.3566542-7-philipp.tomsich@vrull.eu >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-02-16 12:24:18 +10:00
466292bd4a
target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUConfig'
...
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Suggested-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20220202005249.3566542-2-philipp.tomsich@vrull.eu >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-02-16 12:24:18 +10:00
eef11ce325
target/riscv: Remove VILL field in VTYPE
...
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com >
Acked-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20220120122050.41546-18-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-01-21 15:52:57 +10:00
31961cfe50
target/riscv: Adjust vsetvl according to XLEN
...
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20220120122050.41546-17-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-01-21 15:52:57 +10:00
d96a271a8d
target/riscv: Split out the vill from vtype
...
We need not specially process vtype when XLEN changes.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20220120122050.41546-16-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-01-21 15:52:57 +10:00
4208dc7e9e
target/riscv: Split pm_enabled into mask and base
...
Use cached cur_pmmask and cur_pmbase to infer the
current PM mode.
This may decrease the TCG IR by one when pm_enabled
is true and pm_base_enabled is false.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20220120122050.41546-15-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-01-21 15:52:57 +10:00
40bfa5f695
target/riscv: Create current pm fields in env
...
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20220120122050.41546-12-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-01-21 15:52:57 +10:00
440544e1cf
target/riscv: Create xl field in env
...
Current xlen has been used in helper functions and many other places.
The computation of current xlen is not so trivial, so that we should
recompute it as little as possible.
Fortunately, xlen only changes in very seldom cases, such as exception,
misa write, mstatus write, cpu reset, migration load. So that we can only
recompute xlen in this places and cache it into CPURISCVState.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20220120122050.41546-6-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-01-21 15:52:57 +10:00
32e579b8c5
target/riscv: rvv-1.0: Add Zve32f extension into RISC-V
...
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20220118014522.13613-12-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-01-21 15:52:56 +10:00
b4a99d4027
target/riscv: rvv-1.0: Add Zve64f extension into RISC-V
...
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20220118014522.13613-2-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-01-21 15:52:56 +10:00
27abe66f31
target/riscv: Add kvm_riscv_get/put_regs_timer
...
Add kvm_riscv_get/put_regs_timer to synchronize virtual time context
from KVM.
To set register of RISCV_TIMER_REG(state) will occur a error from KVM
on kvm_timer_state == 0. It's better to adapt in KVM, but it doesn't matter
that adaping in QEMU.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com >
Signed-off-by: Mingwang Li <limingwang@huawei.com >
Reviewed-by: Anup Patel <anup.patel@wdc.com >
Acked-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20220112081329.1835-11-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-01-21 15:52:56 +10:00
10f1ca27e0
target/riscv: Add host cpu type
...
'host' type cpu is set isa to RV32 or RV64 simply, more isa info
will obtain from KVM in kvm_arch_init_vcpu()
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com >
Signed-off-by: Mingwang Li <limingwang@huawei.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Anup Patel <anup.patel@wdc.com >
Message-id: 20220112081329.1835-10-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-01-21 15:52:56 +10:00
ad40be2708
target/riscv: Support start kernel directly by KVM
...
Get kernel and fdt start address in virt.c, and pass them to KVM
when cpu reset. Add kvm_riscv.h to place riscv specific interface.
In addition, PLIC is created without M-mode PLIC contexts when KVM
is enabled.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com >
Signed-off-by: Mingwang Li <limingwang@huawei.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Anup Patel <anup@brainfault.org >
Message-id: 20220112081329.1835-7-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-01-21 15:52:56 +10:00
48eaeb56de
target/riscv: Implement the stval/mtval illegal instruction
...
The stval and mtval registers can optionally contain the faulting
instruction on an illegal instruction exception. This patch adds support
for setting the stval and mtval registers.
The RISC-V spec states that "The stval register can optionally also be
used to return the faulting instruction bits on an illegal instruction
exception...". In this case we are always writing the value on an
illegal instruction.
This doesn't match all CPUs (some CPUs won't write the data), but in
QEMU let's just populate the value on illegal instructions. This won't
break any guest software, but will provide more information to guests.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Message-id: 20211220064916.107241-4-alistair.francis@opensource.wdc.com
2022-01-08 15:46:10 +10:00
457c360f9c
target/riscv: actual functions to realize crs 128-bit insns
...
The csrs are accessed through function pointers: we add 128-bit read
operations in the table for three csrs (writes fallback to the
64-bit version as the upper 64-bit information is handled elsewhere):
- misa, as mxl is needed for proper operation,
- mstatus and sstatus, to return sd
In addition, we also add read and write accesses to the machine and
supervisor scratch registers.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr >
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20220106210108.138226-19-frederic.petrot@univ-grenoble-alpes.fr
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-01-08 15:46:10 +10:00
961738ffea
target/riscv: helper functions to wrap calls to 128-bit csr insns
...
Given the side effects they have, the csr instructions are realized as
helpers. We extend this existing infrastructure for 128-bit sized csr.
We return 128-bit values using the same approach as for div/rem.
Theses helpers all call a unique function that is currently a fallback
on the 64-bit version.
The trans_csrxx functions supporting 128-bit are yet to be implemented.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr >
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20220106210108.138226-17-frederic.petrot@univ-grenoble-alpes.fr
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-01-08 15:46:10 +10:00
2c64ab66c1
target/riscv: adding high part of some csrs
...
Adding the high part of a very minimal set of csr.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr >
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20220106210108.138226-16-frederic.petrot@univ-grenoble-alpes.fr
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-01-08 15:46:10 +10:00
b3a5d1fbeb
target/riscv: support for 128-bit M extension
...
Mult are generated inline (using a cool trick pointed out by Richard), but
for div and rem, given the complexity of the implementation of these
instructions, we call helpers to produce their behavior. From an
implementation standpoint, the helpers return the low part of the results,
while the high part is temporarily stored in a dedicated field of cpu_env
that is used to update the architectural register in the generation wrapper.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr >
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20220106210108.138226-15-frederic.petrot@univ-grenoble-alpes.fr
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-01-08 15:46:10 +10:00
332dab6878
target/riscv: setup everything for rv64 to support rv128 execution
...
This patch adds the support of the '-cpu rv128' option to
qemu-system-riscv64 so that we can indicate that we want to run rv128
executables.
Still, there is no support for 128-bit insns at that stage so qemu fails
miserably (as expected) if launched with this option.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr >
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20220106210108.138226-8-frederic.petrot@univ-grenoble-alpes.fr
[ Changed by AF
- Rename CPU to "x-rv128"
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-01-08 15:46:10 +10:00
2b5470843a
target/riscv: array for the 64 upper bits of 128-bit registers
...
The upper 64-bit of the 128-bit registers have now a place inside
the cpu state structure, and are created as globals for future use.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr >
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20220106210108.138226-7-frederic.petrot@univ-grenoble-alpes.fr
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-01-08 15:46:10 +10:00
719d3561b2
target/riscv: gdb: support vector registers for rv64 & rv32
...
Signed-off-by: Hsiangkai Wang <kai.wang@sifive.com >
Signed-off-by: Greentime Hu <greentime.hu@sifive.com >
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Acked-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20211210075704.23951-69-frank.chang@sifive.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-12-20 14:53:31 +10:00
8a4b52575a
target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits
...
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20211210075704.23951-66-frank.chang@sifive.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-12-20 14:53:31 +10:00
a689a82b7f
target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation
...
Update vext_get_vlmax() and MAXSZ() to take fractional LMUL into
calculation for RVV 1.0.
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20211210075704.23951-27-frank.chang@sifive.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-12-20 14:51:36 +10:00
