f87adf23fa
target/riscv: Allow setting CPU feature from machine/device emulation
...
The machine or device emulation should be able to force set certain
CPU features because:
1) We can have certain CPU features which are in-general optional
but implemented by RISC-V CPUs on the machine.
2) We can have devices which require a certain CPU feature. For example,
AIA IMSIC devices expect AIA CSRs implemented by RISC-V CPUs.
Signed-off-by: Anup Patel <anup.patel@wdc.com >
Signed-off-by: Anup Patel <anup@brainfault.org >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Frank Chang <frank.chang@sifive.com >
Message-id: 20220204174700.534953-6-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-02-16 12:24:18 +10:00
cd032fe75c
target/riscv: Implement hgeie and hgeip CSRs
...
The hgeie and hgeip CSRs are required for emulating an external
interrupt controller capable of injecting virtual external interrupt
to Guest/VM running at VS-level.
Signed-off-by: Anup Patel <anup.patel@wdc.com >
Signed-off-by: Anup Patel <anup@brainfault.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Frank Chang <frank.chang@sifive.com >
Message-id: 20220204174700.534953-4-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-02-16 12:24:18 +10:00
881df35d3d
target/riscv: Implement SGEIP bit in hip and hie CSRs
...
A hypervisor can optionally take guest external interrupts using
SGEIP bit of hip and hie CSRs.
Signed-off-by: Anup Patel <anup.patel@wdc.com >
Signed-off-by: Anup Patel <anup@brainfault.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Frank Chang <frank.chang@sifive.com >
Message-id: 20220204174700.534953-3-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-02-16 12:24:18 +10:00
0d429bd243
target/riscv: Add XVentanaCondOps custom extension
...
This adds the decoder and translation for the XVentanaCondOps custom
extension (vendor-defined by Ventana Micro Systems), which is
documented at https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf
This commit then also adds a guard-function (has_XVentanaCondOps_p)
and the decoder function to the table of decoders, enabling the
support for the XVentanaCondOps extension.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20220202005249.3566542-7-philipp.tomsich@vrull.eu >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-02-16 12:24:18 +10:00
6c3a924725
target/riscv: correct "code should not be reached" for x-rv128
...
The addition of uxl support in gdbstub adds a few checks on the maximum
register length, but omitted MXL_RV128, an experimental feature.
This patch makes rv128 react as rv64, as previously.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr >
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20220124202456.420258-1-frederic.petrot@univ-grenoble-alpes.fr
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-02-16 12:24:18 +10:00
5a2ae2350e
target/riscv: Set default XLEN for hypervisor
...
When swap regs for hypervisor, the value of vsstatus or mstatus_hs
should have the right XLEN. Otherwise, it will propagate to mstatus.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20220120122050.41546-22-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-01-21 15:52:57 +10:00
40bfa5f695
target/riscv: Create current pm fields in env
...
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20220120122050.41546-12-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-01-21 15:52:57 +10:00
1191be09a9
target/riscv: Use gdb xml according to max mxlen
...
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20220120122050.41546-9-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-01-21 15:52:57 +10:00
bf9e776ec1
target/riscv: Extend pc for runtime pc write
...
In some cases, we must restore the guest PC to the address of the start of
the TB, such as when the instruction counter hits zero. So extend pc register
according to current xlen for these cases.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20220120122050.41546-8-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-01-21 15:52:57 +10:00
440544e1cf
target/riscv: Create xl field in env
...
Current xlen has been used in helper functions and many other places.
The computation of current xlen is not so trivial, so that we should
recompute it as little as possible.
Fortunately, xlen only changes in very seldom cases, such as exception,
misa write, mstatus write, cpu reset, migration load. So that we can only
recompute xlen in this places and cache it into CPURISCVState.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20220120122050.41546-6-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-01-21 15:52:57 +10:00
2fc1b44dd0
target/riscv: rvv-1.0: Allow Zve32f extension to be turned on
...
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20220118014522.13613-18-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-01-21 15:52:56 +10:00
32e579b8c5
target/riscv: rvv-1.0: Add Zve32f extension into RISC-V
...
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20220118014522.13613-12-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-01-21 15:52:56 +10:00
bfefe406b7
target/riscv: rvv-1.0: Allow Zve64f extension to be turned on
...
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20220118014522.13613-11-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-01-21 15:52:56 +10:00
b4a99d4027
target/riscv: rvv-1.0: Add Zve64f extension into RISC-V
...
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20220118014522.13613-2-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-01-21 15:52:56 +10:00
10f1ca27e0
target/riscv: Add host cpu type
...
'host' type cpu is set isa to RV32 or RV64 simply, more isa info
will obtain from KVM in kvm_arch_init_vcpu()
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com >
Signed-off-by: Mingwang Li <limingwang@huawei.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Anup Patel <anup.patel@wdc.com >
Message-id: 20220112081329.1835-10-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-01-21 15:52:56 +10:00
2b650fbbcc
target/riscv: Support setting external interrupt by KVM
...
When KVM is enabled, set the S-mode external interrupt through
kvm_riscv_set_irq function.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com >
Signed-off-by: Mingwang Li <limingwang@huawei.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Anup Patel <anup.patel@wdc.com >
Message-id: 20220112081329.1835-8-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-01-21 15:52:56 +10:00
ad40be2708
target/riscv: Support start kernel directly by KVM
...
Get kernel and fdt start address in virt.c, and pass them to KVM
when cpu reset. Add kvm_riscv.h to place riscv specific interface.
In addition, PLIC is created without M-mode PLIC contexts when KVM
is enabled.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com >
Signed-off-by: Mingwang Li <limingwang@huawei.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Anup Patel <anup@brainfault.org >
Message-id: 20220112081329.1835-7-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-01-21 15:52:56 +10:00
332dab6878
target/riscv: setup everything for rv64 to support rv128 execution
...
This patch adds the support of the '-cpu rv128' option to
qemu-system-riscv64 so that we can indicate that we want to run rv128
executables.
Still, there is no support for 128-bit insns at that stage so qemu fails
miserably (as expected) if launched with this option.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr >
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20220106210108.138226-8-frederic.petrot@univ-grenoble-alpes.fr
[ Changed by AF
- Rename CPU to "x-rv128"
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-01-08 15:46:10 +10:00
2b5470843a
target/riscv: array for the 64 upper bits of 128-bit registers
...
The upper 64-bit of the 128-bit registers have now a place inside
the cpu state structure, and are created as globals for future use.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr >
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20220106210108.138226-7-frederic.petrot@univ-grenoble-alpes.fr
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-01-08 15:46:10 +10:00
dfdb46a376
target/riscv: Fix position of 'experimental' comment
...
When commit 0643c12e4b0643c12e4bphilipp.tomsich@vrull.eu >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20220106134020.1628889-1-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-01-08 15:46:09 +10:00
07cb270a9a
target/riscv: Enable the Hypervisor extension by default
...
Let's enable the Hypervisor extension by default. This doesn't affect
named CPUs (such as lowrisc-ibex or sifive-u54) but does enable the
Hypervisor extensions by default for the virt machine.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Anup Patel <anup.patel@wdc.com >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Message-Id: <20220105213937.1113508-7-alistair.francis@opensource.wdc.com >
2022-01-08 15:46:09 +10:00
6ca7155a8c
target/riscv: Mark the Hypervisor extension as non experimental
...
The Hypervisor spec is now frozen, so remove the experimental tag.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Anup Patel <anup.patel@wdc.com >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Message-Id: <20220105213937.1113508-6-alistair.francis@opensource.wdc.com >
2022-01-08 15:46:09 +10:00
0643c12e4b
target/riscv: Enable bitmanip Zb[abcs] instructions
...
The bitmanip extension has now been ratified [1] and upstream tooling
(gcc/binutils) support it too, so move them out of experimental and also
enable by default (for better test exposure/coverage)
[1] https://wiki.riscv.org/display/TECH/Recently+Ratified+Extensions
Signed-off-by: Vineet Gupta <vineetg@rivosinc.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20211216051844.3921088-1-vineetg@rivosinc.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-12-20 14:53:31 +10:00
719d3561b2
target/riscv: gdb: support vector registers for rv64 & rv32
...
Signed-off-by: Hsiangkai Wang <kai.wang@sifive.com >
Signed-off-by: Greentime Hu <greentime.hu@sifive.com >
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Acked-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20211210075704.23951-69-frank.chang@sifive.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-12-20 14:53:31 +10:00
9ec6622db3
target/riscv: drop vector 0.7.1 and add 1.0 support
...
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Message-Id: <20211210075704.23951-2-frank.chang@sifive.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-12-20 14:51:36 +10:00
e523773040
target/riscv: zfh: add Zfhmin cpu property
...
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20211210074329.5775-9-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-12-20 14:51:36 +10:00
13fb8c7b42
target/riscv: zfh: add Zfh cpu property
...
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20211210074329.5775-7-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-12-20 14:51:36 +10:00
263e2ab20c
target/riscv: Make riscv_cpu_tlb_fill sysemu only
...
The fallback code in cpu_loop_exit_sigsegv is sufficient
for riscv linux-user.
Remove the code from cpu_loop that raised SIGSEGV.
Reviewed-by: Warner Losh <imp@bsdimp.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2021-11-02 07:00:52 -04:00
0ee9a4e57e
target/riscv: Allow experimental J-ext to be turned on
...
Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20211025173609.2724490-9-space.monkey.delivers@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-10-28 14:39:23 +10:00
bd5594ca28
target/riscv: Print new PM CSRs in QEMU logs
...
Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20211025173609.2724490-6-space.monkey.delivers@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-10-28 14:39:23 +10:00
4bbe8033fc
target/riscv: Support CSRs required for RISC-V PM extension except for the h-mode
...
Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20211025173609.2724490-4-space.monkey.delivers@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-10-28 14:39:23 +10:00
665b90d8a4
target/riscv: Use riscv_csrrw_debug for cpu_dump
...
Use the official debug read interface to the csrs,
rather than referencing the env slots directly.
Put the list of csrs to dump into a table.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20211020031709.359469-15-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-10-22 23:35:47 +10:00
92371bd903
target/riscv: Add MXL/SXL/UXL to TB_FLAGS
...
Begin adding support for switching XLEN at runtime. Extract the
effective XLEN from MISA and MSTATUS and store for use during translation.
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20211020031709.359469-6-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-10-22 07:47:51 +10:00
db23e5d981
target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl
...
Shortly, the set of supported XL will not be just 32 and 64,
and representing that properly using the enumeration will be
imperative.
Two places, booting and gdb, intentionally use misa_mxl_max
to emphasize the use of the reset value of misa.mxl, and not
the current cpu state.
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20211020031709.359469-5-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-10-22 07:47:51 +10:00
e91a7227cb
target/riscv: Split misa.mxl and misa.ext
...
The hw representation of misa.mxl is at the high bits of the
misa csr. Representing this in the same way inside QEMU
results in overly complex code trying to check that field.
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20211020031709.359469-4-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-10-22 07:47:51 +10:00
9d3d60b704
target/riscv: Organise the CPU properties
...
Organise the CPU properties so that standard extensions come first
then followed by experimental extensions.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Message-id: b6598570f60c5ee7f402be56d837bb44b289cc4d.1634531504.git.alistair.francis@wdc.com
2021-10-22 07:47:51 +10:00
e573a7f325
target/riscv: line up all of the registers in the info register dump
...
Ensure the columns for all of the register names and values line up.
No functional change, just a minor tweak to the output.
Signed-off-by: Travis Geiselbrecht <travisg@gmail.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20211009055019.545153-1-travisg@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-10-22 07:47:51 +10:00
9916ea3c97
target/riscv: Remove RVB (replaced by Zb[abcs])
...
With everything classified as Zb[abcs] and pre-0.93 draft-B
instructions that are not part of Zb[abcs] removed, we can remove the
remaining support code for RVB.
Note that RVB has been retired for good and misa.B will neither mean
'some' or 'all of' Zb*:
https://lists.riscv.org/g/tech-bitmanip/message/532
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Message-id: 20210911140016.834071-16-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-10-07 08:41:33 +10:00
878dd0e9ac
target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties
...
The bitmanipulation ISA extensions will be ratified as individual
small extension packages instead of a large B-extension. The first
new instructions through the door (these have completed public review)
are Zb[abcs].
This adds new 'x-zba', 'x-zbb', 'x-zbc' and 'x-zbs' properties for
these in target/riscv/cpu.[ch].
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Message-id: 20210911140016.834071-5-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-10-07 08:32:55 +10:00
0f0b70eeec
target/riscv: Expose interrupt pending bits as GPIO lines
...
Expose the 12 interrupt pending bits in MIP as GPIO lines.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Tested-by: Bin Meng <bmeng.cn@gmail.com >
Message-id: 069d6162f0bc2f4a4f5a44e73f6442b11c703c53.1630301632.git.alistair.francis@wdc.com
2021-09-21 07:56:49 +10:00
a44da25aa6
target/riscv: Update the ePMP CSR address
...
Update the ePMP CSRs to match the 0.9.3 ePMP spec
6145574723/Smepmp/Smepmp.pdfalistair.francis@wdc.com >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Message-id: 28c908de60b9b04fa20e63d113885c98586053f3.1630543194.git.alistair.francis@wdc.com
2021-09-21 07:56:49 +10:00
17b3c353e6
target/riscv: Restrict cpu_exec_interrupt() handler to sysemu
...
Restrict cpu_exec_interrupt() and its callees to sysemu.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Reviewed-by: Warner Losh <imp@bsdimp.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Message-Id: <20210911165434.531552-19-f4bug@amsat.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2021-09-14 12:00:21 -07:00
a8b37120d4
target/riscv: Don't wrongly override isa version
...
For some cpu, the isa version has already been set in cpu init function.
Thus only override the isa version when isa version is not set, or
users set different isa version explicitly by cpu parameters.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Message-id: 20210811144612.68674-1-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-09-01 11:59:12 +10:00
d2c1a177b1
target/riscv: rvb: add b-ext version cpu option
...
Default b-ext version is v0.93.
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20210505160620.15723-18-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-06-08 09:59:46 +10:00
d52e94081e
target/riscv: rvb: support and turn on B-extension from command line
...
B-extension is default off, use cpu rv32 or rv64 with x-b=true to
enable B-extension.
Signed-off-by: Kito Cheng <kito.cheng@sifive.com >
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20210505160620.15723-17-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-06-08 09:59:46 +10:00
a722701dd3
target/riscv: Dump CSR mscratch/sscratch/satp
...
This dumps the CSR mscratch/sscratch/satp and meanwhile aligns
the output of CSR mtval/stval.
Signed-off-by: Changbin Du <changbin.du@gmail.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Message-id: 20210519155738.20486-1-changbin.du@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-06-08 09:59:43 +10:00
9a575d33fb
target/riscv: Remove unnecessary riscv_*_names[] declaration
...
riscv_excp_names[] and riscv_intr_names[] are only referenced by
target/riscv/cpu.c locally.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com >
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20210514052435.2203156-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-06-08 09:59:43 +10:00
119065574d
hw/core: Constify TCGCPUOps
...
We no longer have any runtime modifications to this struct,
so declare them all const.
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-ID: <20210227232519.222663-3-richard.henderson@linaro.org >
2021-05-26 15:33:59 -07:00
08928c6d0d
cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOps
...
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20210517105140.1062037-21-f4bug@amsat.org >
[rth: Drop declaration movement from target/*/cpu.h]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2021-05-26 15:33:59 -07:00
715e3c1afb
cpu: Move CPUClass::write_elf* to SysemuCPUOps
...
The write_elf*() handlers are used to dump vmcore images.
This feature is only meaningful for system emulation.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20210517105140.1062037-19-f4bug@amsat.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2021-05-26 15:33:59 -07:00
