d45a5270d0
Merge remote-tracking branch 'remotes/vivier2/tags/trivial-branch-for-6.1-pull-request' into staging
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Trivial patches pull request 20210503
# gpg: Signature made Mon 03 May 2021 09:34:56 BST
# gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C
# gpg: issuer "laurent@vivier.eu "
# gpg: Good signature from "Laurent Vivier <lvivier@redhat.com >" [full]
# gpg: aka "Laurent Vivier <laurent@vivier.eu >" [full]
# gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com >" [full]
# Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C
* remotes/vivier2/tags/trivial-branch-for-6.1-pull-request: (23 commits)
hw/rx/rx-gdbsim: Do not accept invalid memory size
docs: More precisely describe memory-backend-*::id's user
scripts: fix generation update-binfmts templates
docs/system: Document the removal of "compat" property for POWER CPUs
mc146818rtc: put it into the 'misc' category
Do not include exec/address-spaces.h if it's not really necessary
Do not include cpu.h if it's not really necessary
Do not include hw/boards.h if it's not really necessary
Do not include sysemu/sysemu.h if it's not really necessary
hw: Do not include qemu/log.h if it is not necessary
hw: Do not include hw/irq.h if it is not necessary
hw: Do not include hw/sysbus.h if it is not necessary
hw: Remove superfluous includes of hw/hw.h
ui: Fix memory leak in qemu_xkeymap_mapping_table()
hw/usb: Constify VMStateDescription
hw/display/qxl: Constify VMStateDescription
hw/arm: Constify VMStateDescription
vmstate: Constify some VMStateDescriptions
Fix typo in CFI build documentation
hw/pcmcia: Do not register PCMCIA type if not required
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2021-05-05 13:52:00 +01:00
19f4ed3652
hw: Do not include qemu/log.h if it is not necessary
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Many files include qemu/log.h without needing it. Remove the superfluous
include statements.
Signed-off-by: Thomas Huth <thuth@redhat.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20210328054833.2351597-1-thuth@redhat.com >
Signed-off-by: Laurent Vivier <laurent@vivier.eu >
2021-05-02 17:24:50 +02:00
0d0b91a804
Hexagon (target/hexagon) load and unpack bytes instructions
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The following instructions are added
L2_loadbzw2_io Rd32 = memubh(Rs32+#s11:1)
L2_loadbzw4_io Rdd32 = memubh(Rs32+#s11:1)
L2_loadbsw2_io Rd32 = membh(Rs32+#s11:1)
L2_loadbsw4_io Rdd32 = membh(Rs32+#s11:1)
L4_loadbzw2_ur Rd32 = memubh(Rt32<<#u2+#U6)
L4_loadbzw4_ur Rdd32 = memubh(Rt32<<#u2+#U6)
L4_loadbsw2_ur Rd32 = membh(Rt32<<#u2+#U6)
L4_loadbsw4_ur Rdd32 = membh(Rt32<<#u2+#U6)
L4_loadbzw2_ap Rd32 = memubh(Re32=#U6)
L4_loadbzw4_ap Rdd32 = memubh(Re32=#U6)
L4_loadbsw2_ap Rd32 = membh(Re32=#U6)
L4_loadbsw4_ap Rdd32 = membh(Re32=#U6)
L2_loadbzw2_pr Rd32 = memubh(Rx32++Mu2)
L2_loadbzw4_pr Rdd32 = memubh(Rx32++Mu2)
L2_loadbsw2_pr Rd32 = membh(Rx32++Mu2)
L2_loadbsw4_pr Rdd32 = membh(Rx32++Mu2)
L2_loadbzw2_pbr Rd32 = memubh(Rx32++Mu2:brev)
L2_loadbzw4_pbr Rdd32 = memubh(Rx32++Mu2:brev)
L2_loadbsw2_pbr Rd32 = membh(Rx32++Mu2:brev)
L2_loadbsw4_pbr Rdd32 = membh(Rx32++Mu2:brev)
L2_loadbzw2_pi Rd32 = memubh(Rx32++#s4:1)
L2_loadbzw4_pi Rdd32 = memubh(Rx32++#s4:1)
L2_loadbsw2_pi Rd32 = membh(Rx32++#s4:1)
L2_loadbsw4_pi Rdd32 = membh(Rx32++#s4:1)
L2_loadbzw2_pci Rd32 = memubh(Rx32++#s4:1:circ(Mu2))
L2_loadbzw4_pci Rdd32 = memubh(Rx32++#s4:1:circ(Mu2))
L2_loadbsw2_pci Rd32 = membh(Rx32++#s4:1:circ(Mu2))
L2_loadbsw4_pci Rdd32 = membh(Rx32++#s4:1:circ(Mu2))
L2_loadbzw2_pcr Rd32 = memubh(Rx32++I:circ(Mu2))
L2_loadbzw4_pcr Rdd32 = memubh(Rx32++I:circ(Mu2))
L2_loadbsw2_pcr Rd32 = membh(Rx32++I:circ(Mu2))
L2_loadbsw4_pcr Rdd32 = membh(Rx32++I:circ(Mu2))
Test cases in tests/tcg/hexagon/load_unpack.c
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <1617930474-31979-25-git-send-email-tsimpson@quicinc.com >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2021-05-01 16:06:09 -07:00
46ef47e2a7
Hexagon (target/hexagon) circular addressing
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The following instructions are added
L2_loadrub_pci Rd32 = memub(Rx32++#s4:0:circ(Mu2))
L2_loadrb_pci Rd32 = memb(Rx32++#s4:0:circ(Mu2))
L2_loadruh_pci Rd32 = memuh(Rx32++#s4:1:circ(Mu2))
L2_loadrh_pci Rd32 = memh(Rx32++#s4:1:circ(Mu2))
L2_loadri_pci Rd32 = memw(Rx32++#s4:2:circ(Mu2))
L2_loadrd_pci Rdd32 = memd(Rx32++#s4:3:circ(Mu2))
S2_storerb_pci memb(Rx32++#s4:0:circ(Mu2)) = Rt32
S2_storerh_pci memh(Rx32++#s4:1:circ(Mu2)) = Rt32
S2_storerf_pci memh(Rx32++#s4:1:circ(Mu2)) = Rt.H32
S2_storeri_pci memw(Rx32++#s4:2:circ(Mu2)) = Rt32
S2_storerd_pci memd(Rx32++#s4:3:circ(Mu2)) = Rtt32
S2_storerbnew_pci memb(Rx32++#s4:0:circ(Mu2)) = Nt8.new
S2_storerhnew_pci memw(Rx32++#s4:1:circ(Mu2)) = Nt8.new
S2_storerinew_pci memw(Rx32++#s4:2:circ(Mu2)) = Nt8.new
L2_loadrub_pcr Rd32 = memub(Rx32++I:circ(Mu2))
L2_loadrb_pcr Rd32 = memb(Rx32++I:circ(Mu2))
L2_loadruh_pcr Rd32 = memuh(Rx32++I:circ(Mu2))
L2_loadrh_pcr Rd32 = memh(Rx32++I:circ(Mu2))
L2_loadri_pcr Rd32 = memw(Rx32++I:circ(Mu2))
L2_loadrd_pcr Rdd32 = memd(Rx32++I:circ(Mu2))
S2_storerb_pcr memb(Rx32++I:circ(Mu2)) = Rt32
S2_storerh_pcr memh(Rx32++I:circ(Mu2)) = Rt32
S2_storerf_pcr memh(Rx32++I:circ(Mu2)) = Rt32.H32
S2_storeri_pcr memw(Rx32++I:circ(Mu2)) = Rt32
S2_storerd_pcr memd(Rx32++I:circ(Mu2)) = Rtt32
S2_storerbnew_pcr memb(Rx32++I:circ(Mu2)) = Nt8.new
S2_storerhnew_pcr memh(Rx32++I:circ(Mu2)) = Nt8.new
S2_storerinew_pcr memw(Rx32++I:circ(Mu2)) = Nt8.new
Test cases in tests/tcg/hexagon/circ.c
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <1617930474-31979-23-git-send-email-tsimpson@quicinc.com >
[rth: Squash <1619667142-29636-1-git-send-email-tsimpson@quicinc.com >
removing gen_read_reg and gen_set_byte to avoid clang Werror.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2021-05-01 16:01:39 -07:00
57d352ac29
Hexagon (target/hexagon) add A4_addp_c/A4_subp_c
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Rdd32 = add(Rss32, Rtt32, Px4):carry
Add with carry
Rdd32 = sub(Rss32, Rtt32, Px4):carry
Sub with carry
Test cases in tests/tcg/hexagon/multi_result.c
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <1617930474-31979-22-git-send-email-tsimpson@quicinc.com >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2021-05-01 08:31:43 -07:00
0a65d28693
Hexagon (target/hexagon) add A6_vminub_RdP
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Rdd32,Pe4 = vminub(Rtt32, Rss32)
Vector min of bytes
Test cases in tests/tcg/hexagon/multi_result.c
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <1617930474-31979-21-git-send-email-tsimpson@quicinc.com >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2021-05-01 08:31:43 -07:00
85580a6557
Hexagon (target/hexagon) compile all debug code
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Change #if HEX_DEBUG to if (HEX_DEBUG) so the debug code doesn't bit rot
Suggested-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <1617930474-31979-17-git-send-email-tsimpson@quicinc.com >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2021-05-01 08:31:43 -07:00
a33872eb53
Hexagon (target/hexagon) move QEMU_GENERATE to only be on during macros.h
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Suggested-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <1617930474-31979-16-git-send-email-tsimpson@quicinc.com >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2021-05-01 08:31:43 -07:00
6c677c60ae
Hexagon (target/hexagon) decide if pred has been written at TCG gen time
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Multiple writes to the same preg are and'ed together. Rather than
generating a runtime check, we can determine at TCG generation time
if the predicate has previously been written in the packet.
Test added to tests/tcg/hexagon/misc.c
Suggested-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <1617930474-31979-7-git-send-email-tsimpson@quicinc.com >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2021-05-01 08:31:43 -07:00
edf26ade43
Hexagon (target/hexagon) cleanup gen_log_predicated_reg_write_pair
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Similar to previous cleanup of gen_log_predicated_reg_write
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <1617930474-31979-3-git-send-email-tsimpson@quicinc.com >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2021-05-01 08:31:43 -07:00
d799f8ad08
Hexagon (target/hexagon) TCG generation cleanup
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Simplify TCG generation of hex_reg_written
Suggested-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <1617930474-31979-2-git-send-email-tsimpson@quicinc.com >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2021-05-01 08:31:43 -07:00
57acfcdeb2
Hexagon (target/hexagon) TCG generation
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Include the generated files and set up the data structures
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com >
Message-Id: <1612763186-18161-27-git-send-email-tsimpson@quicinc.com >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2021-02-18 07:48:22 -08:00