99a99c1fc8
target-arm: Add and use symbolic names for register banks
...
Add BANK_<cpumode> #defines to index banked registers.
Suggested-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com >
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-11-03 13:49:41 +00:00
9b539263fa
target-arm: Add support for S1 + S2 MMU translations
...
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com >
Message-id: 1445864527-14520-15-git-send-email-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-10-27 15:59:47 +00:00
a614e69854
target-arm: Add S2 translation to 32bit S1 PTWs
...
Add support for applying S2 translation to 32bit S1
page-table walks.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com >
Message-id: 1445864527-14520-13-git-send-email-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-10-27 15:59:47 +00:00
3778597762
target-arm: Add S2 translation to 64bit S1 PTWs
...
Add support for applying S2 translation to 64bit S1
page-table walks.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com >
Message-id: 1445864527-14520-12-git-send-email-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-10-27 15:59:47 +00:00
e14b5a23d8
target-arm: Add ARMMMUFaultInfo
...
Introduce ARMMMUFaultInfo to propagate MMU Fault information
across the MMU translation code path. This is in preparation for
adding Stage-2 translation.
No functional changes.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com >
Message-id: 1445864527-14520-11-git-send-email-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-10-27 15:59:47 +00:00
af51f566ec
target-arm: Avoid inline for get_phys_addr
...
Avoid inline for get_phys_addr() to prepare for future recursive use.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com >
Message-id: 1445864527-14520-10-git-send-email-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-10-27 15:59:47 +00:00
6ab1a5ee1c
target-arm: Add support for S2 page-table protection bits
...
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com >
Message-id: 1445864527-14520-9-git-send-email-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-10-27 15:59:47 +00:00
1853d5a9dc
target-arm: Add computation of starting level for S2 PTW
...
The starting level for S2 pagetable walks is computed
differently from the S1 starting level. Implement the S2
variant.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com >
Message-id: 1445864527-14520-8-git-send-email-edgar.iglesias@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-10-27 15:59:47 +00:00
973a543482
target-arm: lpae: Rename granule_sz to stride
...
Rename granule_sz to stride to better match the reference manuals.
No functional change.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com >
Message-id: 1445864527-14520-7-git-send-email-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-10-27 15:59:46 +00:00
4ca6a05175
target-arm: lpae: Replace tsz with computed inputsize
...
Remove the tsz variable and introduce inputsize.
This simplifies the code a little and makes it easier to
compare with the reference manuals.
No functional change.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com >
Message-id: 1445864527-14520-6-git-send-email-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-10-27 15:59:46 +00:00
4ee3809801
target-arm: Add support for AArch32 S2 negative t0sz
...
Add support for AArch32 S2 negative t0sz. In preparation for
using 40bit IPAs on AArch32.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com >
Message-id: 1445864527-14520-5-git-send-email-edgar.iglesias@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-10-27 15:59:46 +00:00
1f4c8c18a5
target-arm: lpae: Move declaration of t0sz and t1sz
...
Move declaration of t0sz and t1sz to the top of the function
avoiding a mix of code and variable declarations.
No functional change.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com >
Message-id: 1445864527-14520-4-git-send-email-edgar.iglesias@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-10-27 15:59:46 +00:00
5c31a10d16
target-arm: lpae: Make t0sz and t1sz signed integers
...
Make t0sz and t1sz signed integers to match tsz and to make
it easier to implement support for AArch32 negative t0sz.
t1sz is changed for consistensy.
No functional change.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com >
Message-id: 1445864527-14520-3-git-send-email-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-10-27 15:59:46 +00:00
59e0553073
target-arm: Add HPFAR_EL2
...
Reviewed-by: Alex Bennée <alex.bennee@linaro.org >
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com >
Message-id: 1445864527-14520-2-git-send-email-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-10-27 15:59:46 +00:00
b876452507
target-arm: Add support for SPSR_(ABT|UND|IRQ|FIQ)
...
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com >
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-10-27 12:00:50 +00:00
14cc7b5437
target-arm: Add MDCR_EL2
...
Add the MDCR_EL2 register. We don't implement any of
the debug-related traps this register controls yet, so
currently it simply reads back as written.
Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com >
Message-id: 1444383794-16767-1-git-send-email-serge.fdrv@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
[PMM: tweaked commit message; moved non-dummy definition from
debug_cp_reginfo to el2_cp_reginfo.]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-10-16 13:13:48 +01:00
1424ca8d43
target-arm: Implement AArch64 OSLAR/OSLSR_EL1 sysregs
...
Added oslar_write function to OSLAR_EL1 sysreg, using a status variable
in ARMCPUState.cp15 struct (oslsr_el1). This variable is also linked
to the newly added read-only OSLSR_EL1 register.
Linux reads from this register during its suspend/resume procedure.
Signed-off-by: Davorin Mista <davorin.mista@aggios.com >
[PMM: folded a long line and tweaked a comment]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-10-16 11:14:53 +01:00
2cde031f5a
target-arm: Avoid calling arm_el_is_aa64() function for unimplemented EL
...
It is incorrect to call arm_el_is_aa64() function for unimplemented EL.
This patch fixes several attempts to do so.
Signed-off-by: Sergey Sorokin <afarallax@yandex.ru >
[PMM: Reworked several of the comments to be more verbose.]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-10-16 11:14:52 +01:00
6df99dec9e
target-arm: Break the TB after ISB to execute self-modified code correctly
...
If any store instruction writes the code inside the same TB
after this store insn, the execution of the TB must be stopped
to execute new code correctly.
As described in ARMv8 manual D3.4.6 self-modifying code must do an
IC invalidation to be valid, and an ISB after it. So it's enough to end
the TB after ISB instruction on the code translation.
Also this TB break is necessary to take any pending interrupts immediately
after an ISB (as required by ARMv8 ARM D1.14.4).
Signed-off-by: Sergey Sorokin <afarallax@yandex.ru >
[PMM: tweaked commit message and comments slightly]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-10-16 11:14:52 +01:00
82c39f6a88
target-arm: Add missing 'static' attribute
...
Signed-off-by: Stefan Weil <sw@weilnetz.de >
Message-id: 1443213733-9807-1-git-send-email-sw@weilnetz.de
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-10-16 11:14:52 +01:00
352c98e502
arm: clarify the use of muldiv64()
...
muldiv64() is used to convert microseconds into CPU ticks.
But it is not clear and not commented. This patch uses macro
to clearly identify what is used: time, CPU frequency and ticks.
For an elapsed time and a given frequency, we compute how many ticks
we have.
Signed-off-by: Laurent Vivier <lvivier@redhat.com >
Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com >
Acked-by: Peter Maydell <peter.maydell@linaro.org >
2015-09-25 14:55:21 +02:00
42fedbca8f
target-arm: Use new revbit functions
...
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Richard Henderson <rth@twiddle.net >
2015-09-15 07:45:33 -07:00
f0d574d63f
target-arm: Add VMPIDR_EL2
...
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com >
Message-id: 1442135278-25281-9-git-send-email-edgar.iglesias@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-09-14 14:39:51 +01:00
06a7e6477c
target-arm: Break out mpidr_read_val()
...
Break out mpidr_read_val() to allow future sharing of the
code that conditionally sets the M and U bits of MPIDR.
No functional changes.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com >
Message-id: 1442135278-25281-8-git-send-email-edgar.iglesias@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-09-14 14:39:51 +01:00
731de9e600
target-arm: Add VPIDR_EL2
...
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com >
Message-id: 1442135278-25281-7-git-send-email-edgar.iglesias@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-09-14 14:39:50 +01:00
0c5fbf3b4c
target-arm: Suppress EPD for S2, EL2 and EL3 translations
...
Stage-2 translations, EL2 and EL3 regimes don't have the
EPD control.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com >
Message-id: 1442135278-25281-6-git-send-email-edgar.iglesias@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-09-14 14:39:50 +01:00
1edee4708a
target-arm: Suppress TBI for S2 translations
...
Stage-2 MMU translations do not have configurable TBI as
the top byte is always 0 (48-bit IPAs).
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com >
Message-id: 1442135278-25281-5-git-send-email-edgar.iglesias@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-09-14 14:39:50 +01:00
b698e9cfd2
target-arm: Add VTTBR_EL2
...
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com >
Message-id: 1442135278-25281-4-git-send-email-edgar.iglesias@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-09-14 14:39:50 +01:00
68e9c2fe65
target-arm: Add VTCR_EL2
...
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com >
Message-id: 1442135278-25281-3-git-send-email-edgar.iglesias@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
[PMM: fixed typo in comment]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-09-14 14:39:50 +01:00
97ed5ccdee
tlb: Add "ifetch" argument to cpu_mmu_index()
...
This is set to true when the index is for an instruction fetch
translation.
The core get_page_addr_code() sets it, as do the SOFTMMU_CODE_ACCESS
acessors.
All targets ignore it for now, and all other callers pass "false".
This will allow targets who wish to split the mmu index between
instruction and data accesses to do so. A subsequent patch will
do just that for PowerPC.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org >
Message-Id: <1439796853-4410-2-git-send-email-benh@kernel.crashing.org >
Signed-off-by: Richard Henderson <rth@twiddle.net >
2015-09-11 08:15:28 -07:00
b6af097528
maint: remove / fix many doubled words
...
Many source files have doubled words (eg "the the", "to to",
and so on). Most of these can simply be removed, but a couple
were actual mis-spellings (eg "to to" instead of "to do").
There was even one triple word score "to to to" :-)
Signed-off-by: Daniel P. Berrange <berrange@redhat.com >
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com >
Reviewed-by: Markus Armbruster <armbru@redhat.com >
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru >
2015-09-11 10:21:38 +03:00
c96fc9b52d
target-arm: Add AArch64 access to PAR_EL1
...
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com >
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com >
Message-id: 1441311266-8644-4-git-send-email-edgar.iglesias@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-09-08 17:38:44 +01:00
7a379c7e68
target-arm: Correct opc1 for AT_S12Exx
...
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com >
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com >
Message-id: 1441311266-8644-3-git-send-email-edgar.iglesias@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-09-08 17:38:44 +01:00
3a9148d0bd
target-arm: Fix AArch32:AArch64 general-purpose register mapping
...
There is an error in functions aarch64_sync_32_to_64() and
aarch64_sync_64_to_32() with mapping of registers between AArch32 and
AArch64. This commit fixes the mapping to match the v8 ARM ARM
section D1.20.1 (table D1-77).
Signed-off-by: Sergey Sorokin <afarallax@yandex.ru >
Message-id: 1440796451-15276-1-git-send-email-afarallax@yandex.ru
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
[PMM: tidied commit message a bit]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-09-07 10:39:29 +01:00
8f6fd322f6
arm: Remove hw_error() usages.
...
All of these hw_errors are fatal and indicate something wrong with
QEMU implementation.
Convert to g_assert_not_reached.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com >
Message-id: 169194d09017e5725535d31a1507d454c0043706.1440842587.git.crosthwaite.peter@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-09-07 10:39:29 +01:00
205ace55ff
target-arm: Improve semihosting debug prints
...
Print semihosting debugging information before the
do_arm_semihosting() call so that angel_SWIreason_ReportException,
which causes the function to not return, gets the same debug prints as
other semihosting calls. Also print out the semihosting call number.
Signed-off-by: Christopher Covington <christopher.covington@linaro.org >
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
Tested-by: Christopher Covington <cov@codeaurora.org >
Message-id: 1439483745-28752-3-git-send-email-peter.maydell@linaro.org
2015-09-07 10:39:27 +01:00
cea66e9121
target-arm: Implement AArch64 TLBI operations on IPAs
...
Implement the AArch64 TLBI operations which take an intermediate
physical address and invalidate stage 2 translations.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com >
Message-id: 1439548879-1972-7-git-send-email-peter.maydell@linaro.org
2015-08-25 16:18:33 +01:00
43efaa33fa
target-arm: Implement missing EL3 TLB invalidate operations
...
Implement the remaining stage 1 TLB invalidate operations
visible from EL3.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com >
Message-id: 1439548879-1972-6-git-send-email-peter.maydell@linaro.org
2015-08-25 16:18:33 +01:00
2bfb9d75d3
target-arm: Implement missing EL2 TLBI operations
...
Implement the missing TLBI operations that exist only
if EL2 is implemented.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com >
Message-id: 1439548879-1972-5-git-send-email-peter.maydell@linaro.org
2015-08-25 16:18:33 +01:00
fd3ed96922
target-arm: Restrict AArch64 TLB flushes to the MMU indexes they must touch
...
Now we have the ability to flush the TLB only for specific MMU indexes,
update the AArch64 TLB maintenance instruction implementations to only
flush the parts of the TLB they need to, rather than doing full flushes.
We take the opportunity to remove some duplicate functions (the per-asid
tlb ops work like the non-per-asid ones because we don't support
flushing a TLB only by ASID) and to bring the function names in line
with the architectural TLBI operation names.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com >
Message-id: 1439548879-1972-4-git-send-email-peter.maydell@linaro.org
2015-08-25 16:18:33 +01:00
83ddf97577
target-arm: Move TLBI ALLE1/ALLE1IS definitions into numeric order
...
Move the two regdefs for TLBI ALLE1 and TLBI ALLE1IS down so that the
whole set of AArch64 TLBI regdefs is arranged in numeric order.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com >
Message-id: 1439548879-1972-3-git-send-email-peter.maydell@linaro.org
2015-08-25 16:18:33 +01:00
14db7fe09a
target-arm: Implement AArch32 ATS1H* operations
...
Implement the AArch32 ATS1H* operations which perform
Hyp mode stage 1 translations.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com >
Message-id: 1437751263-21913-6-git-send-email-peter.maydell@linaro.org
2015-08-25 15:45:08 +01:00
87562e4f4a
target-arm: Enable the AArch32 ATS12NSO ops
...
Apply the correct conditions in the ats_access() function for
the ATS12NSO* address translation operations:
* succeed at EL2 or EL3
* normal UNDEF trap from NS EL1
* trap to EL3 from S EL1 (only possible if EL3 is AArch64)
(This change means they're now available in our EL3-supporting
CPUs when they would previously always UNDEF.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com >
Message-id: 1437751263-21913-5-git-send-email-peter.maydell@linaro.org
2015-08-25 15:45:08 +01:00
2a47df9532
target-arm: Wire up AArch64 EL2 and EL3 address translation ops
...
Wire up the AArch64 EL2 and EL3 address translation operations
(AT S12E1*, AT S12E0*, AT S1E2*, AT S1E3*), and correct some
errors in the ats_write64() function in previously unused code
that would have done the wrong kind of lookup for accesses from
EL3 when SCR.NS==0.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com >
Message-id: 1437751263-21913-3-git-send-email-peter.maydell@linaro.org
2015-08-25 15:45:08 +01:00
d0a2cbceb2
target-arm: there is no TTBR1 for 32-bit EL2 stage 1 translations
...
For EL2 stage 1 translations, there is no TTBR1. We were already
handling this for 64-bit EL2; add the code to take the 'no TTBR1'
code path for 64-bit EL2 as well.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com >
Message-id: 1437751263-21913-2-git-send-email-peter.maydell@linaro.org
2015-08-25 15:45:08 +01:00
834a6c6920
target-arm: Implement missing ACTLR registers
...
We already implemented ACTLR_EL1; add the missing ACTLR_EL2 and
ACTLR_EL3, for consistency.
Since we don't currently have any CPUs that need the EL2/EL3
versions to reset to non-zero values, implement as RAZ/WI.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com >
Message-id: 1438281398-18746-5-git-send-email-peter.maydell@linaro.org
2015-08-25 15:45:07 +01:00
37cd6c2478
target-arm: Implement missing AFSR registers
...
The AFSR registers are implementation dependent auxiliary fault
status registers. We already implemented a RAZ/WI AFSR0_EL1 and
AFSR_EL1; add the missing AFSR{0,1}_EL{2,3} for consistency.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com >
Message-id: 1438281398-18746-4-git-send-email-peter.maydell@linaro.org
2015-08-25 15:45:07 +01:00
2179ef958c
target-arm: Implement missing AMAIR registers
...
The AMAIR registers are for providing auxiliary implementation
defined memory attributes. We already implemented a RAZ/WI
AMAIR_EL1; add the EL2 and EL3 versions for consistency.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com >
Message-id: 1438281398-18746-3-git-send-email-peter.maydell@linaro.org
2015-08-25 15:45:07 +01:00
4cfb8ad896
target-arm: Add missing MAIR_EL3 and TPIDR_EL3 registers
...
Add the AArch64 registers MAIR_EL3 and TPIDR_EL3, which are the only
two which we had implemented the 32-bit Secure equivalents of but
not the 64-bit Secure versions.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com >
Message-id: 1438281398-18746-2-git-send-email-peter.maydell@linaro.org
2015-08-25 15:45:07 +01:00
9ff9dd3c87
target-arm: Add AArch32 banked register access to secure physical timer
...
If EL3 is AArch32, then the secure physical timer is accessed via
banking of the registers used for the non-secure physical timer.
Implement this banking.
Note that the access controls for the AArch32 banked registers
remain the same as the physical-timer checks; they are not the
same as the controls on the AArch64 secure timer registers.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
Message-id: 1437047249-2357-3-git-send-email-peter.maydell@linaro.org
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com >
2015-08-13 11:26:22 +01:00
