ed8176a37a
hw/acpi/aml-build: Add aml_create_dword_field() term
...
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com >
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org >
Reviewed-by: Alex Bennée <alex.bennee@linaro.org >
Reviewed-by: Igor Mammedov <imammedo@redhat.com >
Reviewed-by: Michael S. Tsirkin <mst@redhat.com >
Message-id: 1432522520-8068-20-git-send-email-zhaoshenglong@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-05-29 11:28:58 +01:00
467b07dfae
hw/acpi/aml-build: Add aml_else() term
...
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com >
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org >
Reviewed-by: Alex Bennée <alex.bennee@linaro.org >
Reviewed-by: Igor Mammedov <imammedo@redhat.com >
Reviewed-by: Michael S. Tsirkin <mst@redhat.com >
Message-id: 1432522520-8068-19-git-send-email-zhaoshenglong@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-05-29 11:28:58 +01:00
ea7df04a02
hw/acpi/aml-build: Add aml_lnot() term
...
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com >
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org >
Reviewed-by: Alex Bennée <alex.bennee@linaro.org >
Reviewed-by: Igor Mammedov <imammedo@redhat.com >
Reviewed-by: Michael S. Tsirkin <mst@redhat.com >
Message-id: 1432522520-8068-18-git-send-email-zhaoshenglong@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-05-29 11:28:58 +01:00
922cc8823e
hw/acpi/aml-build: Add aml_or() term
...
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com >
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org >
Reviewed-by: Igor Mammedov <imammedo@redhat.com >
Reviewed-by: Michael S. Tsirkin <mst@redhat.com >
Message-id: 1432522520-8068-17-git-send-email-zhaoshenglong@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-05-29 11:28:58 +01:00
b930fb9db4
hw/acpi/aml-build: Add ToUUID macro
...
Add ToUUID macro, this is useful for generating PCIe ACPI table.
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com >
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org >
Reviewed-by: Igor Mammedov <imammedo@redhat.com >
Reviewed-by: Michael S. Tsirkin <mst@redhat.com >
Message-id: 1432522520-8068-16-git-send-email-zhaoshenglong@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-05-29 11:28:57 +01:00
ed8b5847e4
hw/acpi/aml-build: Make aml_buffer() definition consistent with the spec
...
According to ACPI spec, DefBuffer can take two parameters: BufferSize
and ByteList. Make it consistent with the spec. Uninitialized buffer
could be requested by passing ByteList as NULL to reserve space.
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com >
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org >
Reviewed-by: Igor Mammedov <imammedo@redhat.com >
Reviewed-by: Michael S. Tsirkin <mst@redhat.com >
Message-id: 1432522520-8068-15-git-send-email-zhaoshenglong@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-05-29 11:28:57 +01:00
8434488400
hw/arm/virt-acpi-build: Generate MCFG table
...
Generate MCFG table for PCIe controller.
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com >
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org >
Reviewed-by: Alex Bennée <alex.bennee@linaro.org >
Message-id: 1432522520-8068-14-git-send-email-zhaoshenglong@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-05-29 11:28:57 +01:00
d4bec5d876
hw/arm/virt-acpi-build: Generate RSDP table
...
RSDP points to RSDT which in turn points to other tables.
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com >
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org >
Reviewed-by: Alex Bennée <alex.bennee@linaro.org >
Message-id: 1432522520-8068-13-git-send-email-zhaoshenglong@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-05-29 11:28:56 +01:00
243bdb79fb
hw/arm/virt-acpi-build: Generate RSDT table
...
RSDT points to other tables FADT, MADT, GTDT. This code is shared with x86.
Here we still use RSDT as UEFI puts ACPI tables below 4G address space,
and UEFI ignore the RSDT or XSDT.
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com >
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org >
Reviewed-by: Alex Bennée <alex.bennee@linaro.org >
Message-id: 1432522520-8068-12-git-send-email-zhaoshenglong@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-05-29 11:28:56 +01:00
ee246400c1
hw/arm/virt-acpi-build: Generate GTDT table
...
ACPI v5.1 defines GTDT for ARM devices as a place to describe timer
related information in the system. The Arch Timer interrupts must
be provided for GTDT.
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com >
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org >
Reviewed-by: Alex Bennée <alex.bennee@linaro.org >
Message-id: 1432522520-8068-11-git-send-email-zhaoshenglong@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-05-29 11:28:56 +01:00
982d06c561
hw/arm/virt-acpi-build: Generate MADT table
...
MADT describes GIC enabled ARM platforms. The GICC and GICD
subtables are used to define the GIC regions.
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com >
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org >
Reviewed-by: Alex Bennée <alex.bennee@linaro.org >
Message-id: 1432522520-8068-10-git-send-email-zhaoshenglong@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-05-29 11:28:56 +01:00
c2f7c0c306
hw/arm/virt-acpi-build: Generate FADT table and update ACPI headers
...
In the case of mach virt, it is used to set the Hardware Reduced bit
and enable PSCI SMP booting through HVC. So ignore FACS and FADT
points to DSDT.
Update the header definitions for FADT taking into account the new
additions of ACPI v5.1 in `include/hw/acpi/acpi-defs.h`
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com >
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org >
Message-id: 1432522520-8068-9-git-send-email-zhaoshenglong@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-05-29 11:28:55 +01:00
dfccd8cfd7
hw/arm/virt-acpi-build: Generation of DSDT table for virt devices
...
DSDT consists of the usual common table header plus a definition
block in AML encoding which describes all devices in the platform.
After initializing DSDT with header information the namespace is
created which is followed by the device encodings. The devices are
described using the Resource Template for the 32-Bit Fixed Memory
Range and the Extended Interrupt Descriptors.
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com >
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org >
Reviewed-by: Alex Bennée <alex.bennee@linaro.org >
Message-id: 1432522520-8068-8-git-send-email-zhaoshenglong@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-05-29 11:28:55 +01:00
205d1d1c04
hw/acpi/aml-build: Add aml_interrupt() term
...
Add aml_interrupt() for describing device interrupt in resource template.
These can be used to generating DSDT table for ACPI on ARM.
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com >
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org >
Reviewed-by: Igor Mammedov <imammedo@redhat.com >
Message-id: 1432522520-8068-7-git-send-email-zhaoshenglong@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-05-29 11:28:55 +01:00
dc17ab1de5
hw/acpi/aml-build: Add aml_memory32_fixed() term
...
Add aml_memory32_fixed() for describing device mmio region in resource
template. These can be used to generating DSDT table for ACPI on ARM.
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com >
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org >
Reviewed-by: Alex Bennée <alex.bennee@linaro.org >
Reviewed-by: Igor Mammedov <imammedo@redhat.com >
Reviewed-by: Michael S. Tsirkin <mst@redhat.com >
Message-id: 1432522520-8068-6-git-send-email-zhaoshenglong@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-05-29 11:28:55 +01:00
f5d8c8cd79
hw/arm/virt-acpi-build: Basic framework for building ACPI tables on ARM
...
Introduce a preliminary framework in virt-acpi-build.c with the main
ACPI build functions. It exposes the generated ACPI contents to
guest over fw_cfg.
The required ACPI v5.1 tables for ARM are:
- RSDP: Initial table that points to XSDT
- RSDT: Points to FADT GTDT MADT tables
- FADT: Generic information about the machine
- GTDT: Generic timer description table
- MADT: Multiple APIC description table
- DSDT: Holds all information about system devices/peripherals, pointed by FADT
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com >
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org >
Reviewed-by: Alex Bennée <alex.bennee@linaro.org >
Reviewed-by: Igor Mammedov <imammedo@redhat.com >
Message-id: 1432522520-8068-5-git-send-email-zhaoshenglong@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-05-29 11:28:54 +01:00
6a1f001be3
hw/arm/virt: Record PCIe ranges in MemMapEntry array
...
To generate ACPI table for PCIe controller, we need the base and size of
the PCIe ranges. Record these ranges in MemMapEntry array, then we could
share and use them for generating ACPI table.
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com >
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org >
Message-id: 1432522520-8068-4-git-send-email-zhaoshenglong@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-05-29 11:28:54 +01:00
afe0b3803f
hw/arm/virt: Move common definitions to virt.h
...
Move some common definitions to virt.h. These will be used by
generating ACPI tables.
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com >
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org >
Reviewed-by: Alex Bennée <alex.bennee@linaro.org >
Message-id: 1432522520-8068-3-git-send-email-zhaoshenglong@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-05-29 11:28:54 +01:00
ff80dc7fa8
hw/acpi/aml-build: Make enum values to be upper case to match coding style
...
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com >
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org >
Reviewed-by: Igor Mammedov <imammedo@redhat.com >
Message-id: 1432522520-8068-2-git-send-email-zhaoshenglong@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-05-29 11:28:54 +01:00
9441aa282b
Merge remote-tracking branch 'remotes/kraxel/tags/pull-input-20150529-1' into staging
...
kbd: add support for brazilian keyboard (two extra keys).
input: add virtio-input devices.
# gpg: Signature made Fri May 29 10:09:02 2015 BST using RSA key ID D3E87138
# gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com >"
# gpg: aka "Gerd Hoffmann <gerd@kraxel.org >"
# gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com >"
* remotes/kraxel/tags/pull-input-20150529-1:
virtio-input: emulated devices [device]
virtio-input: core code & base class [device]
virtio-input: add linux/input.h
kbd: add brazil kbd keys to x11 evdev map
kbd: add brazil kbd keys to qemu
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-05-29 11:23:07 +01:00
55a1d80a41
virtio-input: emulated devices [device]
...
This patch adds the virtio-input-hid base class and
virtio-{keyboard,mouse,tablet} subclasses building on the base class.
They are hooked up to the qemu input core and deliver input events
to the guest like all other hid devices (ps/2 kbd, usb tablet, ...).
Using them is as simple as adding "-device virtio-tablet-device" to
your command line, for use all transports except pci. virtio-pci
support comes as separate patch, once virtio-pci got virtio 1.0
support.
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com >
2015-05-29 10:30:40 +02:00
f73ddbad39
virtio-input: core code & base class [device]
...
This patch adds virtio-input support to qemu. It brings a abstract
base class providing core support, other classes can build on it to
actually implement input devices.
virtio-input basically sends linux input layer events (evdev) over
virtio.
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com >
2015-05-29 10:30:26 +02:00
641381c1fc
spice: don't update mm_time when spice-server is stopped.
...
Skip mm_time updates (in qxl device memory) in case the guest is stopped.
Guest isn't able to look anyway, and it causes problems with migration.
Also make sure the initial state for spice server is stopped.
Reported-by: Dr. David Alan Gilbert <dgilbert@redhat.com >
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com >
2015-05-29 09:56:01 +02:00
246ca55faf
virtio-console: notify chardev when writable
...
When the virtio serial is writable, notify the chardev backend
with qemu_chr_accept_input().
Signed-off-by: Marc-André Lureau <marcandre.lureau@gmail.com >
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com >
2015-05-29 09:56:01 +02:00
0915aed584
Merge remote-tracking branch 'remotes/jnsnow/tags/ide-pull-request' into staging
...
# gpg: Signature made Fri May 22 20:58:44 2015 BST using RSA key ID AAFC390E
# gpg: Good signature from "John Snow (John Huston) <jsnow@redhat.com >"
# gpg: WARNING: This key is not certified with sufficiently trusted signatures!
# gpg: It is not certain that the signature belongs to the owner.
# Primary key fingerprint: FAEB 9711 A12C F475 812F 18F2 88A9 064D 1835 61EB
# Subkey fingerprint: F9B7 ABDB BCAC DF95 BE76 CBD0 7DEF 8106 AAFC 390E
* remotes/jnsnow/tags/ide-pull-request:
ahci: do not remap clb/fis unconditionally
macio: move unaligned DMA write code into separate pmac_dma_write() function
macio: move unaligned DMA read code into separate pmac_dma_read() function
qtest: pre-buffer hex nibs
libqos/ahci: Swap memread/write with bufread/write
qtest: add memset to qtest protocol
qtest: Add base64 encoded read/write
qtest: allow arbitrarily long sends
qtest/ahci: add migrate halted dma test
qtest/ahci: add halted dma test
qtest/ahci: add flush migrate test
qtest/ahci: add migrate dma test
qtest/ahci: Add migration test
ich9/ahci: Enable Migration
libqos: Add migration helpers
libqos/ahci: Fix sector set method
libqos/ahci: Add halted command helpers
glib: remove stale compat functions
configure: require glib 2.22
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-05-26 11:31:03 +01:00
cd6cb73beb
ahci: do not remap clb/fis unconditionally
...
This continues the IOMMU fix from 2.3, where we should not attempt
to remap the CLB or FIS RX buffers if the AHCI device is currently
running.
The same applies to migration: keep our mitts off these registers
unless the device is supposed to be on.
Does not impact backwards compatibility for the AHCI device.
Signed-off-by: John Snow <jsnow@redhat.com >
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com >
Message-id: 1431470173-30847-2-git-send-email-jsnow@redhat.com
2015-05-22 15:58:22 -04:00
bd4214fc92
macio: move unaligned DMA write code into separate pmac_dma_write() function
...
Similarly switch the macio IDE routines over to use the new function and
tidy-up the remaining code as required.
[Maintainer edit: printf format codes adjusted for 32/64bit. --js]
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk >
Acked-by: John Snow <jsnow@redhat.com >
Message-id: 1425939893-14404-3-git-send-email-mark.cave-ayland@ilande.co.uk
Signed-off-by: John Snow <jsnow@redhat.com >
2015-05-22 15:58:22 -04:00
4827ac1e8f
macio: move unaligned DMA read code into separate pmac_dma_read() function
...
This considerably helps simplify the complexity of the macio read routines and
by switching macio CDROM accesses to use the new code, fixes the issue with
the CDROM device being detected intermittently by Darwin/OS X.
[Maintainer edit: printf format codes adjusted for 32/64bit. --js]
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ailande.co.uk >
Acked-by: John Snow <jsnow@redhat.com >
Message-id: 1425939893-14404-2-git-send-email-mark.cave-ayland@ilande.co.uk
Signed-off-by: John Snow <jsnow@redhat.com >
2015-05-22 15:58:22 -04:00
04329029a8
ich9/ahci: Enable Migration
...
Lift the flag preventing the migration of the ICH9/AHCI devices.
Signed-off-by: John Snow <jsnow@redhat.com >
Reviewed-by: Kevin Wolf <kwolf@redhat.com >
Message-id: 1430417242-11859-5-git-send-email-jsnow@redhat.com
2015-05-22 15:58:22 -04:00
aacd5650c6
nvme: support NVME_VOLATILE_WRITE_CACHE feature
...
The SCSI emulation in the Linux NVMe driver really wants to know
if a device has a volatile write cache. Given that qemu has moved
away from a model where we report the backing store WCE bit to
one where the WCE bit is supposed to be part of the migratable
guest-visible state we always return 1 here.
Signed-off-by: Christoph Hellwig <hch@lst.de >
Acked-by: Keith Busch <keith.busch@intel.com >
Signed-off-by: Kevin Wolf <kwolf@redhat.com >
2015-05-22 17:08:00 +02:00
eba05e922e
Merge remote-tracking branch 'remotes/kraxel/tags/pull-serial-20150519-1' into staging
...
serial: fix multi-pci card error cleanup.
# gpg: Signature made Tue May 19 11:47:29 2015 BST using RSA key ID D3E87138
# gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com >"
# gpg: aka "Gerd Hoffmann <gerd@kraxel.org >"
# gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com >"
* remotes/kraxel/tags/pull-serial-20150519-1:
serial: fix multi-pci card error cleanup.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-05-19 14:10:33 +01:00
a48da7b5bc
serial: fix multi-pci card error cleanup.
...
Put the number of serial ports into a local variable in
multi_serial_pci_realize, then increment the port count
(pci->ports) as we initialize the serial port cores.
Now pci->ports always holds the number of successfully
initialized ports and we can use multi_serial_pci_exit
to properly cleanup the already initialized bits in case
of a init failure.
https://bugzilla.redhat.com/show_bug.cgi?id=970551
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com >
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com >
2015-05-19 12:47:08 +02:00
176c324feb
vga-pci: QOMify
...
Signed-off-by: Gonglei <arei.gonglei@huawei.com >
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com >
2015-05-19 11:40:01 +02:00
c69f6c7dcf
qxl: QOMify
...
Signed-off-by: Gonglei <arei.gonglei@huawei.com >
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com >
2015-05-19 11:40:01 +02:00
d338bae33a
cirrus_vga: QOMify
...
QOMify pci-cirrus-vga like isa-cirrus-vga device.
Signed-off-by: Gonglei <arei.gonglei@huawei.com >
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com >
2015-05-19 11:40:01 +02:00
082587b741
arm: xlnx-ep108: Add bootloading
...
Add bootloader support using standard ARM bootloader.
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com >
Tested-by: Alistair Francis <alistair.francis@xilinx.com >
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com >
Message-id: b829abaf2b70d02b28e79301553cbd74afc416a1.1431381507.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-05-18 16:41:14 +01:00
b79b9d28f6
arm: xlnx-ep108: Add external RAM
...
Zynq MPSoC supports external DDR RAM. Add a RAM at 0 to the model.
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com >
Tested-by: Alistair Francis <alistair.francis@xilinx.com >
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com >
Message-id: 2c25e2a4198402a6477aef2975d5df7c415dd341.1431381507.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-05-18 16:41:14 +01:00
859a0c5b5f
arm: Add xlnx-ep108 machine
...
Add a machine model for the Xilinx ZynqMP SoC EP108 board.
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com >
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com >
Tested-by: Alistair Francis <alistair.francis@xilinx.com >
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com >
Message-id: 3896b34c862f370dc0679e4428bf3848d1f9f83c.1431381507.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-05-18 16:41:13 +01:00
3bade2a9e6
arm: xlnx-zynqmp: Add UART support
...
There are 2x Cadence UARTs in Zynq MP. Add them.
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com >
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Tested-by: Alistair Francis <alistair.francis@xilinx.com >
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com >
Message-id: e30795536f77599fabc1052278d846ccd52322e2.1431381507.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-05-18 16:41:13 +01:00
8ae57b2fa3
char: cadence_uart: Split state struct and type into header
...
Create a new header for Cadence UART to allow using the device with
modern SoC programming conventions. The state struct needs to be
visible to embed the device in SoC containers.
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com >
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com >
Tested-by: Alistair Francis <alistair.francis@xilinx.com >
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com >
Message-id: 46a0fbd45b6b205f54c4a8c778deb75c77f8abdf.1431381507.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-05-18 16:41:12 +01:00
e86da3cb40
char: cadence_uart: Clean up variable names
...
Clean up some variable names in preparation for migrating the state struct
and type cast macro to a public header. The acronym "UART" on it's own is
not specific enough to be used in a more global namespace so preface with
"cadence". Fix the capitalisation of "uart" in the state type while touching
the typename. Preface macros used by the state struct itself with CADENCE_UART
so they don't conflict in namespace either.
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com >
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com >
Tested-by: Alistair Francis <alistair.francis@xilinx.com >
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com >
Message-id: 3812b7426c338beae9e082557f3524a99310ddc6.1431381507.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-05-18 16:41:12 +01:00
14ca2e462e
arm: xlnx-zynqmp: Add GEM support
...
There are 4x Cadence GEMs in ZynqMP. Add them.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Tested-by: Alistair Francis <alistair.francis@xilinx.com >
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com >
Message-id: 7d3e68e5495d145255f0ee567046415e3a26d67e.1431381507.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-05-18 16:41:11 +01:00
f49856d4e6
net: cadence_gem: Split state struct and type into header
...
Create a new header for Cadence GEM to allow using the device with
modern SoC programming conventions. The state struct needs to be
visible to embed the device in SoC containers.
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com >
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com >
Tested-by: Alistair Francis <alistair.francis@xilinx.com >
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com >
Message-id: a98b5df6440c5bff8f813a26bb53ce1cfefb4c4c.1431381507.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-05-18 16:41:11 +01:00
448f19e231
net: cadence_gem: Clean up variable names
...
Cleanup some variable names in preparation for migrating the state
struct and type cast macro to a public header. The acronym "GEM" on
its own is not specific enough to be used in a more global namespace
so preface with "cadence". Fix the capitalisation of "gem" in the
state type while touching the typename. Also preface the GEM_MAXREG
macro as this will need to migrate to public header.
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com >
Reviewed-by: Alex Bennée <alex.bennee@linaro.org >
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com >
Tested-by: Alistair Francis <alistair.francis@xilinx.com >
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com >
Message-id: 8e2b0687b3a7b7a3fde5ba2f3bee6f3b911e84ef.1431381507.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-05-18 16:41:10 +01:00
bf4cb10966
arm: xlnx-zynqmp: Connect CPU Timers to GIC
...
Connect the GPIO outputs from the individual CPUs for the timers to the
GIC.
Tested-by: Alistair Francis <alistair.francis@xilinx.com >
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com >
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com >
Message-id: a7866a4f0c903c91fa3034210b4d2879aa4bfcb9.1431381507.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-05-18 16:41:10 +01:00
7729e1f4b3
arm: xlnx-zynqmp: Add GIC
...
Add the GIC and connect IRQ outputs to the CPUs. The GIC regions are
under-decoded through a 64k address region so implement aliases
accordingly.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com >
Message-id: 5853189965728d676106d9e94e76b9bb87981cb5.1431381507.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-05-18 16:41:09 +01:00
f0a902f764
arm: Introduce Xilinx ZynqMP SoC
...
With quad Cortex-A53 CPUs.
Use SMC PSCI, with the standard policy of secondaries starting in
power-off.
Tested-by: Alistair Francis <alistair.francis@xilinx.com >
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com >
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com >
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com >
Message-id: a16202a6c7b79e446e5289d38cb18d2ee4b897a0.1431381507.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-05-18 16:41:09 +01:00
e907746266
fdc: force the fifo access to be in bounds of the allocated buffer
...
During processing of certain commands such as FD_CMD_READ_ID and
FD_CMD_DRIVE_SPECIFICATION_COMMAND the fifo memory access could
get out of bounds leading to memory corruption with values coming
from the guest.
Fix this by making sure that the index is always bounded by the
allocated memory.
This is CVE-2015-3456.
Signed-off-by: Petr Matousek <pmatouse@redhat.com >
Reviewed-by: John Snow <jsnow@redhat.com >
Signed-off-by: John Snow <jsnow@redhat.com >
2015-05-12 18:52:57 -04:00
5ae79fe825
hw/arm/highbank.c: Wire FIQ between CPU <> GIC
...
Connect FIQ output of the GIC CPU interfaces to the CPUs.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
Message-id: 1430502643-25909-18-git-send-email-peter.maydell@linaro.org
2015-05-12 11:57:19 +01:00
27192e390d
hw/arm/vexpress.c: Wire FIQ between CPU <> GIC
...
Connect FIQ output of the GIC CPU interfaces to the CPUs.
Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch >
Signed-off-by: Greg Bellows <greg.bellows@linaro.org >
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com >
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
Message-id: 1430502643-25909-17-git-send-email-peter.maydell@linaro.org
Message-id: 1429113742-8371-3-git-send-email-greg.bellows@linaro.org
[PMM: minor format tweak]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2015-05-12 11:57:18 +01:00
