6d56e39649
hw/riscv/virt: Connect the gpex PCIe
...
Connect the gpex PCIe device based on the device tree included in the
HiFive Unleashed ROM.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Logan Gunthorpe <logang@deltatee.com >
Reviewed-by: Logan Gunthorpe <logang@deltatee.com >
Tested-by: Guenter Roeck <linux@roeck-us.net >
Tested-by: Andrea Bolognani <abologna@redhat.com >
Signed-off-by: Palmer Dabbelt <palmer@sifive.com >
2018-12-20 11:45:20 -08:00
63b695f2aa
hw/riscv/virt: Increase the number of interrupts
...
Increase the number of interrupts to match the HiFive Unleashed board.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Tested-by: Guenter Roeck <linux@roeck-us.net >
Tested-by: Andrea Bolognani <abologna@redhat.com >
Signed-off-by: Palmer Dabbelt <palmer@sifive.com >
2018-12-20 11:45:20 -08:00
5b5583806b
RISC-V: Make virt header comment title consistent
...
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu >
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de >
Signed-off-by: Michael Clark <mjc@sifive.com >
Signed-off-by: Palmer Dabbelt <palmer@sifive.com >
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
2018-05-06 10:39:38 +12:00
4996b12874
RISC-V: Make some header guards more specific
...
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu >
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de >
Signed-off-by: Michael Clark <mjc@sifive.com >
Signed-off-by: Palmer Dabbelt <palmer@sifive.com >
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
2018-05-06 10:39:38 +12:00
42b3a4b7cc
RISC-V: Remove unused class definitions
...
Removes a whole lot of unnecessary boilerplate code. Machines
don't need to be objects. The expansion of the SOC object model
for the RISC-V machines will happen in the future as SiFive
plans to add their FE310 and FU540 SOCs to QEMU. However, it
seems that this present boilerplate is complete unnecessary.
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu >
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de >
Signed-off-by: Michael Clark <mjc@sifive.com >
Signed-off-by: Palmer Dabbelt <palmer@sifive.com >
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
2018-05-06 10:39:38 +12:00
6b01e3277e
RISC-V: Use ROM base address and size from memmap
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Another case of replacing hard coded constants, this time
referring to the definition in the virt machine's memmap.
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu >
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de >
Signed-off-by: Michael Clark <mjc@sifive.com >
Signed-off-by: Palmer Dabbelt <palmer@sifive.com >
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
2018-05-06 10:39:38 +12:00
2a8756ed7d
RISC-V: Replace hardcoded constants with enum values
...
The RISC-V device-tree code has a number of hard-coded
constants and this change moves them into header enums.
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu >
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de >
Signed-off-by: Michael Clark <mjc@sifive.com >
Signed-off-by: Palmer Dabbelt <palmer@sifive.com >
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
2018-05-06 10:39:38 +12:00
04331d0b56
RISC-V VirtIO Machine
...
RISC-V machine with device-tree, 16550a UART and VirtIO MMIO.
The following machine is implemented:
- 'virt'; CLINT, PLIC, 16550A UART, VirtIO MMIO, device-tree
Acked-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: Palmer Dabbelt <palmer@sifive.com >
Signed-off-by: Michael Clark <mjc@sifive.com >
2018-03-07 08:30:28 +13:00
