24018cf399
target/arm: Implement fp16 for Neon VCVT fixed-point
...
Implement fp16 for the Neon VCVT insns which convert between
float and fixed-point.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20200828183354.27913-39-peter.maydell@linaro.org
2020-09-01 11:38:50 +01:00
7b959c5890
target/arm: Convert Neon VCVT fixed-point to gvec
...
Convert the Neon VCVT float<->fixed-point insns to a
gvec style, in preparation for adding fp16 support.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20200828183354.27913-38-peter.maydell@linaro.org
2020-09-01 11:38:42 +01:00
7782a9afec
target/arm: Implement fp16 for Neon float-integer VCVT
...
Convert the Neon float-integer VCVT insns to gvec, and use this
to implement fp16 support for them.
Note that unlike the VFP int<->fp16 VCVT insns we converted
earlier and which convert to/from a 32-bit integer, these
Neon insns convert to/from 16-bit integers. So we can use
the existing vfp conversion helpers for the f32<->u32/i32
case but need to provide our own for f16<->u16/i16.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20200828183354.27913-37-peter.maydell@linaro.org
2020-09-01 11:38:35 +01:00
1dc587ee9b
target/arm: Implement fp16 for Neon pairwise fp ops
...
Convert the Neon pairwise fp ops to use a single gvic-style
helper to do the full operation instead of one helper call
for each 32-bit part. This allows us to use the same
framework to implement the fp16.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20200828183354.27913-36-peter.maydell@linaro.org
2020-09-01 11:38:20 +01:00
40fde72dda
target/arm: Implement fp16 for Neon VRSQRTS
...
Convert the Neon VRSQRTS insn to using a gvec helper,
and use this to implement the fp16 case.
As with VRECPS, we adjust the phrasing of the new implementation
slightly so that the fp32 version parallels the fp16 one.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20200828183354.27913-35-peter.maydell@linaro.org
2020-09-01 11:38:13 +01:00
ac8c62c4e5
target/arm: Implement fp16 for Neon VRECPS
...
Convert the Neon VRECPS insn to using a gvec helper, and
use this to implement the fp16 case.
The phrasing of the new float32_recps_nf() is slightly different from
the old recps_f32() so that it parallels the f16 version; for f16 we
can't assume that flush-to-zero is always enabled.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20200828183354.27913-34-peter.maydell@linaro.org
2020-09-01 11:38:06 +01:00
635187aaa9
target/arm: Implement fp16 for Neon fp compare-vs-0
...
Convert the neon floating-point vector compare-vs-0 insns VCEQ0,
VCGT0, VCLE0, VCGE0 and VCLT0 to use a gvec helper, and use this to
implement the fp16 case.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20200828183354.27913-33-peter.maydell@linaro.org
2020-09-01 11:37:59 +01:00
cf722d75b3
target/arm: Implement fp16 for Neon VFMA, VMFS
...
Convert the neon floating-point vector operations VFMA and VFMS
to use a gvec helper, and use this to implement the fp16 case.
This is the last use of do_3same_fp() so we can now delete
that function.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20200828183354.27913-32-peter.maydell@linaro.org
2020-09-01 11:37:51 +01:00
e5adc70665
target/arm: Implement fp16 for Neon VMLA, VMLS operations
...
Convert the Neon floating-point VMLA and VMLS insns over to using a
gvec helper, and use this to implement the fp16 case.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20200828183354.27913-31-peter.maydell@linaro.org
2020-09-01 11:31:48 +01:00
e22705bb94
target/arm: Implement fp16 for Neon VMAXNM, VMINNM
...
Convert the Neon floating point VMAXNM and VMINNM insns to
using a gvec helper and use this to implement the fp16 case.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20200828183354.27913-30-peter.maydell@linaro.org
2020-09-01 11:31:16 +01:00
e43268c54b
target/arm: Implement fp16 for Neon VMAX, VMIN
...
Convert the Neon float-point VMAX and VMIN insns over to using
a gvec helper, and use this to implement the fp16 case.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20200828183354.27913-29-peter.maydell@linaro.org
2020-09-01 11:31:12 +01:00
bb2741da18
target/arm: Implement fp16 for VACGE, VACGT
...
Convert the neon floating-point vector absolute comparison ops
VACGE and VACGT over to using a gvec hepler and use this to
implement the fp16 case.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20200828183354.27913-28-peter.maydell@linaro.org
2020-09-01 11:31:05 +01:00
ad505db233
target/arm: Implement fp16 for VCEQ, VCGE, VCGT comparisons
...
Convert the Neon floating-point vector comparison ops VCEQ,
VCGE and VCGT over to using a gvec helper and use this to
implement the fp16 case.
(We put the float16_ceq() etc functions above the DO_2OP()
macro definition because later when we convert the
compare-against-zero instructions we'll want their
definitions to be visible at that point in the source file.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20200828183354.27913-27-peter.maydell@linaro.org
2020-09-01 11:30:58 +01:00
e4a6d4a69e
target/arm: Implement FP16 for Neon VADD, VSUB, VABD, VMUL
...
Implement FP16 support for the Neon insns which use the DO_3S_FP_GVEC
macro: VADD, VSUB, VABD, VMUL.
For VABD this requires us to implement a new gvec_fabd_h helper
using the machinery we have already for the other helpers.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20200828183354.27913-24-peter.maydell@linaro.org
2020-09-01 11:19:32 +01:00
ed78849d97
target/arm: Convert sq{, r}dmulh to gvec for aa64 advsimd
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Message-id: 20200815013145.539409-21-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2020-08-28 10:02:50 +01:00
3607440c4d
target/arm: Convert integer multiply-add (indexed) to gvec for aa64 advsimd
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Message-id: 20200815013145.539409-20-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2020-08-28 10:02:50 +01:00
2e5a265e6a
target/arm: Convert integer multiply (indexed) to gvec for aa64 advsimd
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Message-id: 20200815013145.539409-19-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2020-08-28 10:02:50 +01:00
d21798856b
target/arm: Generalize inl_qrdmlah_* helper functions
...
Unify add/sub helpers and add a parameter for rounding.
This will allow saturating non-rounding to reuse this code.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
[PMM: fixed accidental use of '=' rather than '+=' in do_sqrdmlah_s]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Message-id: 20200815013145.539409-15-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2020-08-28 10:02:49 +01:00
a04b68e1d4
target/arm: Convert aes and sm4 to gvec helpers
...
With this conversion, we will be able to use the same helpers
with sve. In particular, pass 3 vector parameters for the
3-operand operations; for advsimd the destination register
is also an input.
This also fixes a bug in which we failed to clear the high bits
of the SVE register after an AdvSIMD operation.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20200514212831.31248-2-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2020-06-05 17:23:09 +01:00
a26a352bb4
target/arm: Convert Neon VADD, VSUB, VABD 3-reg-same insns to decodetree
...
Convert the Neon VADD, VSUB, VABD 3-reg-same insns to decodetree.
We already have gvec helpers for addition and subtraction, but must
add one for fabd.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20200512163904.10918-12-peter.maydell@linaro.org
2020-05-14 15:03:09 +01:00
cfdb2c0c95
target/arm: Vectorize SABA/UABA
...
Include 64-bit element size in preparation for SVE2.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20200513163245.17915-17-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2020-05-14 15:03:08 +01:00
50c160d44e
target/arm: Vectorize SABD/UABD
...
Include 64-bit element size in preparation for SVE2.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20200513163245.17915-16-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2020-05-14 15:03:08 +01:00
525d9b6d42
target/arm: Clear tail in gvec_fmul_idx_*, gvec_fmla_idx_*
...
Must clear the tail for AdvSIMD when SVE is enabled.
Fixes: ca40a6e6e3qemu-stable@nongnu.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20200513163245.17915-15-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2020-05-14 15:03:08 +01:00
e286bf4a72
target/arm: Pass pointer to qc to qrdmla/qrdmls
...
Pass a pointer directly to env->vfp.qc[0], rather than env.
This will allow SVE2, which does not modify QC, to pass a
pointer to dummy storage.
Change the return type of inl_qrdml.h_s16 to match the
sense of the operation: signed.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20200513163245.17915-14-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2020-05-14 15:03:08 +01:00
893ab0542a
target/arm: Create gen_gvec_{sri,sli}
...
The functions eliminate duplication of the special cases for
this operation. They match up with the GVecGen2iFn typedef.
Add out-of-line helpers. We got away with only having inline
expanders because the neon vector size is only 16 bytes, and
we know that the inline expansion will always succeed.
When we reuse this for SVE, tcg-gvec-op may decide to use an
out-of-line helper due to longer vector lengths.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20200513163245.17915-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2020-05-14 15:03:08 +01:00
6ccd48d4ea
target/arm: Create gen_gvec_{u,s}{rshr,rsra}
...
Create vectorized versions of handle_shri_with_rndacc
for shift+round and shift+round+accumulate. Add out-of-line
helpers in preparation for longer vector lengths from SVE.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20200513163245.17915-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2020-05-14 15:03:08 +01:00
631e565450
target/arm: Create gen_gvec_[us]sra
...
The functions eliminate duplication of the special cases for
this operation. They match up with the GVecGen2iFn typedef.
Add out-of-line helpers. We got away with only having inline
expanders because the neon vector size is only 16 bytes, and
we know that the inline expansion will always succeed.
When we reuse this for SVE, tcg-gvec-op may decide to use an
out-of-line helper due to longer vector lengths.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20200513163245.17915-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2020-05-14 15:03:08 +01:00
6b375d3546
target/arm: Vectorize integer comparison vs zero
...
These instructions are often used in glibc's string routines.
They were the final uses of the 32-bit at a time neon helpers.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20200418162808.4680-1-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2020-04-30 15:35:41 +01:00
e7e96fc5ec
target/arm: Convert PMULL.8 to gvec
...
We still need two different helpers, since NEON and SVE2 get the
inputs from different locations within the source vector. However,
we can convert both to the same internal form for computation.
The sve2 helper is not used yet, but adding it with this patch
helps illustrate why the neon changes are helpful.
Tested-by: Alex Bennée <alex.bennee@linaro.org >
Reviewed-by: Alex Bennée <alex.bennee@linaro.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20200216214232.4230-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2020-02-21 16:07:02 +00:00
b9ed510e46
target/arm: Convert PMULL.64 to gvec
...
The gvec form will be needed for implementing SVE2.
Tested-by: Alex Bennée <alex.bennee@linaro.org >
Reviewed-by: Alex Bennée <alex.bennee@linaro.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20200216214232.4230-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2020-02-21 16:07:02 +00:00
a21bb78e58
target/arm: Convert PMUL.8 to gvec
...
The gvec form will be needed for implementing SVE2.
Extend the implementation to operate on uint64_t instead of uint32_t.
Use a counted inner loop instead of terminating when op1 goes to zero,
looking toward the required implementation for ARMv8.4-DIT.
Tested-by: Alex Bennée <alex.bennee@linaro.org >
Reviewed-by: Alex Bennée <alex.bennee@linaro.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20200216214232.4230-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2020-02-21 16:07:02 +00:00
87b74e8b6e
target/arm: Vectorize USHL and SSHL
...
These instructions shift left or right depending on the sign
of the input, and 7 bits are significant to the shift. This
requires several masks and selects in addition to the actual
shifts to form the complete answer.
That said, the operation is still a small improvement even for
two 64-bit elements -- 13 vector operations instead of 2 * 7
integer operations.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20200216214232.4230-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2020-02-21 16:07:02 +00:00
a4e943a716
target/arm: Add helpers for FMLAL
...
Note that float16_to_float32 rightly squashes SNaN to QNaN.
But of course pickNaNMulAdd, for ARM, selects SNaNs first.
So we have to preserve SNaN long enough for the correct NaN
to be selected. Thus float16_to_float32_by_bits.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20190219222952.22183-2-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2019-02-28 11:03:05 +00:00
d8efe78e80
target/arm: Add missing clear_tail calls
...
Fortunately, the functions affected are so far only called from SVE,
so there is no tail to be cleared. But as we convert more of AdvSIMD
to gvec, this will matter.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20190209033847.9014-13-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2019-02-15 09:56:41 +00:00
89e68b575e
target/arm: Use vector operations for saturation
...
For same-sign saturation, we have tcg vector operations. We can
compute the QC bit by comparing the saturated value against the
unsaturated value.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20190209033847.9014-12-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2019-02-15 09:56:41 +00:00
a4d5846245
target/arm: Split out FPSCR.QC to a vector field
...
Change the representation of this field such that it is easy
to set from vector code.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20190209033847.9014-11-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2019-02-15 09:56:41 +00:00
16fcfdc732
target/arm: Implement SVE dot product (indexed)
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Reviewed-by: Alex Bennée <alex.bennee@linaro.org >
Message-id: 20180627043328.11531-34-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2018-06-29 15:11:15 +01:00
d730ecaae7
target/arm: Implement SVE dot product (vectors)
...
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20180627043328.11531-33-richard.henderson@linaro.org
[PMM: moved 'ra=%reg_movprfx' here from following patch]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2018-06-29 15:11:13 +01:00
18fc240578
target/arm: Implement SVE fp complex multiply add (indexed)
...
Enhance the existing helpers to support SVE, which takes the
index from each 128-bit segment. The change has no effect
for AdvSIMD, since there is only one such segment.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Reviewed-by: Alex Bennée <alex.bennee@linaro.org >
Message-id: 20180627043328.11531-32-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2018-06-29 15:11:12 +01:00
2cc99919a8
target/arm: Pass index to AdvSIMD FCMLA (indexed)
...
For aa64 advsimd, we had been passing the pre-indexed vector.
However, sve applies the index to each 128-bit segment, so we
need to pass in the index separately.
For aa32 advsimd, the fp32 operation always has index 0, but
we failed to interpret the fp16 index correctly.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Reviewed-by: Alex Bennée <alex.bennee@linaro.org >
Message-id: 20180627043328.11531-31-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2018-06-29 15:11:12 +01:00
3887c0388d
target/arm: Implement SVE Floating Point Unary Operations - Unpredicated Group
...
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20180627043328.11531-21-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2018-06-29 15:11:09 +01:00
ca40a6e6e3
target/arm: Implement SVE Floating Point Multiply Indexed Group
...
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20180627043328.11531-19-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2018-06-29 15:11:08 +01:00
29b80469dc
target/arm: Implement SVE Floating Point Arithmetic - Unpredicated Group
...
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20180613015641.5667-19-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2018-06-15 15:23:34 +01:00
23c11b04dc
target: Do not include "exec/exec-all.h" if it is not necessary
...
Code change produced with:
$ git grep '#include "exec/exec-all.h"' | \
cut -d: -f-1 | \
xargs egrep -L "(cpu_address_space_init|cpu_loop_|tlb_|tb_|GETPC|singlestep|TranslationBlock)" | \
xargs sed -i.bak '/#include "exec\/exec-all.h"/d'
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Message-Id: <20180528232719.4721-10-f4bug@amsat.org >
Acked-by: Michael S. Tsirkin <mst@redhat.com >
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com >
2018-06-01 14:15:10 +02:00
d17b7cdcf4
target/arm: Decode aa64 armv8.3 fcmla
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20180228193125.20577-13-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
[PMM: renamed e1/e2/e3/e4 to use the same naming as the version
of the pseudocode in the Arm ARM]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
2018-03-02 11:03:45 +00:00
1695cd61b0
target/arm: Decode aa64 armv8.3 fcadd
...
Reviewed-by: Alex Bennée <alex.bennee@linaro.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20180228193125.20577-12-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2018-03-02 11:03:45 +00:00
e7186d8229
target/arm: Decode aa64 armv8.1 three same extra
...
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20180228193125.20577-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2018-03-02 11:03:45 +00:00
d9061ec3d2
target/arm: Decode aa64 armv8.1 scalar three same extra
...
Reviewed-by: Alex Bennée <alex.bennee@linaro.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20180228193125.20577-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2018-03-02 11:03:45 +00:00
