3bf03f0899
hw/riscv: Allow creating multiple instances of CLINT
...
We extend CLINT emulation to allow multiple instances of CLINT in
a QEMU RISC-V machine. To achieve this, we remove first HART id
zero assumption from CLINT emulation.
Signed-off-by: Anup Patel <anup.patel@wdc.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com >
Message-Id: <20200616032229.766089-2-anup.patel@wdc.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2020-08-25 09:11:35 -07:00
5f3616ccce
hw/riscv: Provide rdtime callback for TCG in CLINT emulation
...
This patch extends CLINT emulation to provide rdtime callback for
TCG. This rdtime callback will be called wheneven TIME CSRs are
read in privileged modes.
Signed-off-by: Anup Patel <anup.patel@wdc.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com >
2020-02-27 13:46:37 -08:00
ec150c7e09
include: Make headers more self-contained
...
Back in 2016, we discussed[1] rules for headers, and these were
generally liked:
1. Have a carefully curated header that's included everywhere first. We
got that already thanks to Peter: osdep.h.
2. Headers should normally include everything they need beyond osdep.h.
If exceptions are needed for some reason, they must be documented in
the header. If all that's needed from a header is typedefs, put
those into qemu/typedefs.h instead of including the header.
3. Cyclic inclusion is forbidden.
This patch gets include/ closer to obeying 2.
It's actually extracted from my "[RFC] Baby steps towards saner
headers" series[2], which demonstrates a possible path towards
checking 2 automatically. It passes the RFC test there.
[1] Message-ID: <87h9g8j57d.fsf@blackfin.pond.sub.org >
https://lists.nongnu.org/archive/html/qemu-devel/2016-03/msg03345.html
[2] Message-Id: <20190711122827.18970-1-armbru@redhat.com >
https://lists.nongnu.org/archive/html/qemu-devel/2019-07/msg02715.html
Signed-off-by: Markus Armbruster <armbru@redhat.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20190812052359.30071-2-armbru@redhat.com >
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com >
2019-08-16 13:31:51 +02:00
2a8756ed7d
RISC-V: Replace hardcoded constants with enum values
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The RISC-V device-tree code has a number of hard-coded
constants and this change moves them into header enums.
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu >
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de >
Signed-off-by: Michael Clark <mjc@sifive.com >
Signed-off-by: Palmer Dabbelt <palmer@sifive.com >
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
2018-05-06 10:39:38 +12:00
1c77c410b6
SiFive RISC-V CLINT Block
...
The CLINT (Core Local Interruptor) device provides real-time clock, timer
and interprocessor interrupts based on SiFive's CLINT specification.
Acked-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: Sagar Karandikar <sagark@eecs.berkeley.edu >
Signed-off-by: Stefan O'Rear <sorear2@gmail.com >
Signed-off-by: Palmer Dabbelt <palmer@sifive.com >
Signed-off-by: Michael Clark <mjc@sifive.com >
2018-03-07 08:30:28 +13:00
