6b4c305cbd
fpu: move public header file to include/fpu
...
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com >
2012-12-19 08:32:46 +01:00
14cccb6185
qom: move include files to include/qom/
...
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com >
2012-12-19 08:31:32 +01:00
022c62cbbc
exec: move include files to include/exec/
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com >
2012-12-19 08:31:31 +01:00
7b1b5d1913
qapi: move include files to include/qobject/
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com >
2012-12-19 08:31:31 +01:00
44e04d3b94
target-openrisc: remove conflicting definitions from cpu.h
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On an ARM host, the registers definitions from cpu.h clash
with /usr/include/sys/ucontext.h. As there are unused, just remove
them.
Cc: Jia Liu <proljc@gmail.com >
Cc: qemu-stable@nongnu.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net >
2012-11-24 13:19:54 +01:00
3993c6bddf
cpus: Pass CPUState to [qemu_]cpu_has_work()
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For target-mips also change the return type to bool.
Make include paths for cpu-qom.h consistent for alpha and unicore32.
Signed-off-by: Andreas Färber <afaerber@suse.de >
[AF: Updated new target-openrisc function accordingly]
Acked-by: Richard Henderson <rth@twiddle.net > (for alpha)
2012-10-31 04:11:37 +01:00
a8170e5e97
Rename target_phys_addr_t to hwaddr
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target_phys_addr_t is unwieldly, violates the C standard (_t suffixes are
reserved) and its purpose doesn't match the name (most target_phys_addr_t
addresses are not target specific). Replace it with a finger-friendly,
standards conformant hwaddr.
Outstanding patchsets can be fixed up with the command
git rebase -i --exec 'find -name "*.[ch]"
| xargs s/target_phys_addr_t/hwaddr/g' origin
Signed-off-by: Avi Kivity <avi@redhat.com >
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com >
2012-10-23 08:58:25 -05:00
d962783e98
target-or32: Add linux user support
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Add QEMU OpenRISC linux user support.
Signed-off-by: Jia Liu <proljc@gmail.com >
Signed-off-by: Blue Swirl <blauwirbel@gmail.com >
2012-07-27 21:13:05 +00:00
4dd044c6ba
target-or32: Add system instructions
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Add OpenRISC system instructions.
Signed-off-by: Jia Liu <proljc@gmail.com >
Signed-off-by: Blue Swirl <blauwirbel@gmail.com >
2012-07-27 21:13:03 +00:00
99f575edcc
target-or32: Add timer support
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Add OpenRISC timer support.
Signed-off-by: Jia Liu <proljc@gmail.com >
Signed-off-by: Blue Swirl <blauwirbel@gmail.com >
2012-07-27 21:13:02 +00:00
dd29c7fb01
target-or32: Add PIC support
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Add OpenRISC Programmable Interrupt Controller support.
Signed-off-by: Jia Liu <proljc@gmail.com >
Signed-off-by: Blue Swirl <blauwirbel@gmail.com >
2012-07-27 21:13:01 +00:00
b6a71ef7e0
target-or32: Add interrupt support
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Add OpenRISC interrupt support.
Signed-off-by: Jia Liu <proljc@gmail.com >
Signed-off-by: Blue Swirl <blauwirbel@gmail.com >
2012-07-27 21:12:57 +00:00
726fe04572
target-or32: Add MMU support
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Add OpenRISC MMU support.
Signed-off-by: Jia Liu <proljc@gmail.com >
Signed-off-by: Blue Swirl <blauwirbel@gmail.com >
2012-07-27 21:12:56 +00:00
e67db06e9f
target-or32: Add target stubs and QOM cpu
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Add OpenRISC target stubs, QOM cpu and basic machine.
Signed-off-by: Jia Liu <proljc@gmail.com >
Signed-off-by: Blue Swirl <blauwirbel@gmail.com >
2012-07-27 21:12:55 +00:00
