mirror of
https://github.com/mii443/qemu.git
synced 2025-12-11 06:58:34 +00:00
Merge branch 'ppc-for-upstream' of git://github.com/agraf/qemu
* 'ppc-for-upstream' of git://github.com/agraf/qemu: (58 commits)
target-ppc: Use NARROW_MODE macro for tlbie
target-ppc: Use NARROW_MODE macro for addresses
target-ppc: Use NARROW_MODE macro for comparisons
target-ppc: Use NARROW_MODE macro for branches
target-ppc: Fix add and subf carry generation in narrow mode
target-ppc: Use QOM method dispatch for MMU fault handling
target-ppc: Move ppc tlb_fill implementation into mmu_helper.c
target-ppc: Split user only code out of mmu_helper.c
mmu-hash64: Implement Virtual Page Class Key Protection
mmu-hash*: Merge translate and fault handling functions
mmu-hash*: Don't use full ppc_hash{32, 64}_translate() path for get_phys_page_debug()
mmu-hash*: Correctly mask RPN from hash PTE
mmu-hash*: Clean up real address calculation
mmu-hash*: Clean up PTE flags update
mmu-hash64: Factor SLB N bit into permissions bits
mmu-hash*: Clean up permission checking
mmu-hash32: Remove nx from context structure
mmu-hash*: Don't update PTE flags when permission is denied
mmu-hash32: Don't look up page tables on BAT permission error
mmu-hash32: Cleanup BAT lookup
...
This commit is contained in:
Aurelien Jarno
@@ -629,7 +629,7 @@ static void ppc_spapr_reset(void)
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spapr->rtas_size);
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/* Set up the entry state */
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first_cpu_cpu = CPU(first_cpu);
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first_cpu_cpu = ENV_GET_CPU(first_cpu);
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first_cpu->gpr[3] = spapr->fdt_addr;
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first_cpu->gpr[5] = 0;
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first_cpu_cpu->halted = 0;
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@@ -779,6 +779,11 @@ static void ppc_spapr_init(QEMUMachineInitArgs *args)
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spapr->htab_shift++;
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}
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/* Set up Interrupt Controller before we create the VCPUs */
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spapr->icp = xics_system_init(smp_cpus * kvmppc_smt_threads() / smp_threads,
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XICS_IRQS);
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spapr->next_irq = XICS_IRQ_BASE;
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/* init CPUs */
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if (cpu_model == NULL) {
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cpu_model = kvm_enabled() ? "host" : "POWER7";
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@@ -791,6 +796,8 @@ static void ppc_spapr_init(QEMUMachineInitArgs *args)
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}
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env = &cpu->env;
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xics_cpu_setup(spapr->icp, cpu);
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/* Set time-base frequency to 512 MHz */
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cpu_ppc_tb_init(env, TIMEBASE_FREQ);
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@@ -830,11 +837,6 @@ static void ppc_spapr_init(QEMUMachineInitArgs *args)
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}
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g_free(filename);
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/* Set up Interrupt Controller */
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spapr->icp = xics_system_init(XICS_IRQS);
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spapr->next_irq = XICS_IRQ_BASE;
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/* Set up EPOW events infrastructure */
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spapr_events_init(spapr);
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@@ -856,7 +858,7 @@ static void ppc_spapr_init(QEMUMachineInitArgs *args)
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/* Set up PCI */
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spapr_pci_rtas_init();
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phb = spapr_create_phb(spapr, 0, "pci");
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phb = spapr_create_phb(spapr, 0);
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for (i = 0; i < nb_nics; i++) {
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NICInfo *nd = &nd_table[i];
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@@ -3,39 +3,7 @@
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#include "sysemu/sysemu.h"
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#include "helper_regs.h"
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#include "hw/spapr.h"
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#define HPTES_PER_GROUP 8
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#define HPTE_V_SSIZE_SHIFT 62
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#define HPTE_V_AVPN_SHIFT 7
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#define HPTE_V_AVPN 0x3fffffffffffff80ULL
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#define HPTE_V_AVPN_VAL(x) (((x) & HPTE_V_AVPN) >> HPTE_V_AVPN_SHIFT)
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#define HPTE_V_COMPARE(x, y) (!(((x) ^ (y)) & 0xffffffffffffff80UL))
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#define HPTE_V_BOLTED 0x0000000000000010ULL
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#define HPTE_V_LOCK 0x0000000000000008ULL
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#define HPTE_V_LARGE 0x0000000000000004ULL
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#define HPTE_V_SECONDARY 0x0000000000000002ULL
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#define HPTE_V_VALID 0x0000000000000001ULL
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#define HPTE_R_PP0 0x8000000000000000ULL
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#define HPTE_R_TS 0x4000000000000000ULL
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#define HPTE_R_KEY_HI 0x3000000000000000ULL
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#define HPTE_R_RPN_SHIFT 12
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#define HPTE_R_RPN 0x3ffffffffffff000ULL
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#define HPTE_R_FLAGS 0x00000000000003ffULL
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#define HPTE_R_PP 0x0000000000000003ULL
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#define HPTE_R_N 0x0000000000000004ULL
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#define HPTE_R_G 0x0000000000000008ULL
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#define HPTE_R_M 0x0000000000000010ULL
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#define HPTE_R_I 0x0000000000000020ULL
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#define HPTE_R_W 0x0000000000000040ULL
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#define HPTE_R_WIMG 0x0000000000000078ULL
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#define HPTE_R_C 0x0000000000000080ULL
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#define HPTE_R_R 0x0000000000000100ULL
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#define HPTE_R_KEY_LO 0x0000000000000e00ULL
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#define HPTE_V_1TB_SEG 0x4000000000000000ULL
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#define HPTE_V_VRMA_MASK 0x4001ffffff000000ULL
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#include "mmu-hash64.h"
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static target_ulong compute_tlbie_rb(target_ulong v, target_ulong r,
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target_ulong pte_index)
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@@ -44,17 +12,17 @@ static target_ulong compute_tlbie_rb(target_ulong v, target_ulong r,
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rb = (v & ~0x7fULL) << 16; /* AVA field */
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va_low = pte_index >> 3;
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if (v & HPTE_V_SECONDARY) {
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if (v & HPTE64_V_SECONDARY) {
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va_low = ~va_low;
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}
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/* xor vsid from AVA */
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if (!(v & HPTE_V_1TB_SEG)) {
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if (!(v & HPTE64_V_1TB_SEG)) {
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va_low ^= v >> 12;
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} else {
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va_low ^= v >> 24;
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}
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va_low &= 0x7ff;
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if (v & HPTE_V_LARGE) {
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if (v & HPTE64_V_LARGE) {
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rb |= 1; /* L field */
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#if 0 /* Disable that P7 specific bit for now */
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if (r & 0xff000) {
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@@ -84,10 +52,10 @@ static target_ulong h_enter(PowerPCCPU *cpu, sPAPREnvironment *spapr,
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target_ulong page_shift = 12;
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target_ulong raddr;
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target_ulong i;
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uint8_t *hpte;
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hwaddr hpte;
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/* only handle 4k and 16M pages for now */
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if (pteh & HPTE_V_LARGE) {
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if (pteh & HPTE64_V_LARGE) {
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#if 0 /* We don't support 64k pages yet */
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if ((ptel & 0xf000) == 0x1000) {
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/* 64k page */
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@@ -105,11 +73,11 @@ static target_ulong h_enter(PowerPCCPU *cpu, sPAPREnvironment *spapr,
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}
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}
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raddr = (ptel & HPTE_R_RPN) & ~((1ULL << page_shift) - 1);
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raddr = (ptel & HPTE64_R_RPN) & ~((1ULL << page_shift) - 1);
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if (raddr < spapr->ram_limit) {
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/* Regular RAM - should have WIMG=0010 */
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if ((ptel & HPTE_R_WIMG) != HPTE_R_M) {
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if ((ptel & HPTE64_R_WIMG) != HPTE64_R_M) {
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return H_PARAMETER;
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}
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} else {
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@@ -117,7 +85,7 @@ static target_ulong h_enter(PowerPCCPU *cpu, sPAPREnvironment *spapr,
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/* FIXME: What WIMG combinations could be sensible for IO?
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* For now we allow WIMG=010x, but are there others? */
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/* FIXME: Should we check against registered IO addresses? */
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if ((ptel & (HPTE_R_W | HPTE_R_I | HPTE_R_M)) != HPTE_R_I) {
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if ((ptel & (HPTE64_R_W | HPTE64_R_I | HPTE64_R_M)) != HPTE64_R_I) {
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return H_PARAMETER;
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}
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}
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@@ -129,26 +97,26 @@ static target_ulong h_enter(PowerPCCPU *cpu, sPAPREnvironment *spapr,
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}
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if (likely((flags & H_EXACT) == 0)) {
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pte_index &= ~7ULL;
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hpte = env->external_htab + (pte_index * HASH_PTE_SIZE_64);
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hpte = pte_index * HASH_PTE_SIZE_64;
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for (i = 0; ; ++i) {
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if (i == 8) {
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return H_PTEG_FULL;
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}
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if ((ldq_p(hpte) & HPTE_V_VALID) == 0) {
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if ((ppc_hash64_load_hpte0(env, hpte) & HPTE64_V_VALID) == 0) {
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break;
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}
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hpte += HASH_PTE_SIZE_64;
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}
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} else {
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i = 0;
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hpte = env->external_htab + (pte_index * HASH_PTE_SIZE_64);
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if (ldq_p(hpte) & HPTE_V_VALID) {
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hpte = pte_index * HASH_PTE_SIZE_64;
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if (ppc_hash64_load_hpte0(env, hpte) & HPTE64_V_VALID) {
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return H_PTEG_FULL;
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}
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}
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stq_p(hpte + (HASH_PTE_SIZE_64/2), ptel);
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ppc_hash64_store_hpte1(env, hpte, ptel);
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/* eieio(); FIXME: need some sort of barrier for smp? */
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stq_p(hpte, pteh);
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ppc_hash64_store_hpte0(env, hpte, pteh);
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args[0] = pte_index + i;
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return H_SUCCESS;
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@@ -166,26 +134,26 @@ static target_ulong remove_hpte(CPUPPCState *env, target_ulong ptex,
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target_ulong flags,
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target_ulong *vp, target_ulong *rp)
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{
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uint8_t *hpte;
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hwaddr hpte;
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target_ulong v, r, rb;
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if ((ptex * HASH_PTE_SIZE_64) & ~env->htab_mask) {
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return REMOVE_PARM;
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}
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hpte = env->external_htab + (ptex * HASH_PTE_SIZE_64);
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hpte = ptex * HASH_PTE_SIZE_64;
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v = ldq_p(hpte);
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r = ldq_p(hpte + (HASH_PTE_SIZE_64/2));
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v = ppc_hash64_load_hpte0(env, hpte);
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r = ppc_hash64_load_hpte1(env, hpte);
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if ((v & HPTE_V_VALID) == 0 ||
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if ((v & HPTE64_V_VALID) == 0 ||
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((flags & H_AVPN) && (v & ~0x7fULL) != avpn) ||
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((flags & H_ANDCOND) && (v & avpn) != 0)) {
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return REMOVE_NOT_FOUND;
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}
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*vp = v;
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*rp = r;
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stq_p(hpte, 0);
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ppc_hash64_store_hpte0(env, hpte, 0);
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rb = compute_tlbie_rb(v, r, ptex);
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ppc_tlb_invalidate_one(env, rb);
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return REMOVE_SUCCESS;
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@@ -271,7 +239,7 @@ static target_ulong h_bulk_remove(PowerPCCPU *cpu, sPAPREnvironment *spapr,
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switch (ret) {
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case REMOVE_SUCCESS:
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*tsh |= (r & (HPTE_R_C | HPTE_R_R)) << 43;
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*tsh |= (r & (HPTE64_R_C | HPTE64_R_R)) << 43;
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break;
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case REMOVE_PARM:
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@@ -292,34 +260,34 @@ static target_ulong h_protect(PowerPCCPU *cpu, sPAPREnvironment *spapr,
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target_ulong flags = args[0];
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target_ulong pte_index = args[1];
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target_ulong avpn = args[2];
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uint8_t *hpte;
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hwaddr hpte;
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target_ulong v, r, rb;
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if ((pte_index * HASH_PTE_SIZE_64) & ~env->htab_mask) {
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return H_PARAMETER;
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}
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hpte = env->external_htab + (pte_index * HASH_PTE_SIZE_64);
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hpte = pte_index * HASH_PTE_SIZE_64;
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v = ldq_p(hpte);
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r = ldq_p(hpte + (HASH_PTE_SIZE_64/2));
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v = ppc_hash64_load_hpte0(env, hpte);
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r = ppc_hash64_load_hpte1(env, hpte);
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if ((v & HPTE_V_VALID) == 0 ||
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if ((v & HPTE64_V_VALID) == 0 ||
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((flags & H_AVPN) && (v & ~0x7fULL) != avpn)) {
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return H_NOT_FOUND;
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}
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r &= ~(HPTE_R_PP0 | HPTE_R_PP | HPTE_R_N |
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HPTE_R_KEY_HI | HPTE_R_KEY_LO);
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r |= (flags << 55) & HPTE_R_PP0;
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r |= (flags << 48) & HPTE_R_KEY_HI;
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r |= flags & (HPTE_R_PP | HPTE_R_N | HPTE_R_KEY_LO);
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r &= ~(HPTE64_R_PP0 | HPTE64_R_PP | HPTE64_R_N |
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HPTE64_R_KEY_HI | HPTE64_R_KEY_LO);
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r |= (flags << 55) & HPTE64_R_PP0;
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r |= (flags << 48) & HPTE64_R_KEY_HI;
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r |= flags & (HPTE64_R_PP | HPTE64_R_N | HPTE64_R_KEY_LO);
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rb = compute_tlbie_rb(v, r, pte_index);
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stq_p(hpte, v & ~HPTE_V_VALID);
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ppc_hash64_store_hpte0(env, hpte, v & ~HPTE64_V_VALID);
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ppc_tlb_invalidate_one(env, rb);
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stq_p(hpte + (HASH_PTE_SIZE_64/2), r);
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ppc_hash64_store_hpte1(env, hpte, r);
|
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/* Don't need a memory barrier, due to qemu's global lock */
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stq_p(hpte, v);
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ppc_hash64_store_hpte0(env, hpte, v);
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return H_SUCCESS;
|
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}
|
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|
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|
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@@ -521,46 +521,39 @@ static void xics_reset(void *opaque)
|
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}
|
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}
|
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|
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struct icp_state *xics_system_init(int nr_irqs)
|
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void xics_cpu_setup(struct icp_state *icp, PowerPCCPU *cpu)
|
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{
|
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CPUState *cs = CPU(cpu);
|
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CPUPPCState *env = &cpu->env;
|
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struct icp_server_state *ss = &icp->ss[cs->cpu_index];
|
||||
|
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assert(cs->cpu_index < icp->nr_servers);
|
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|
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switch (PPC_INPUT(env)) {
|
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case PPC_FLAGS_INPUT_POWER7:
|
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ss->output = env->irq_inputs[POWER7_INPUT_INT];
|
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break;
|
||||
|
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case PPC_FLAGS_INPUT_970:
|
||||
ss->output = env->irq_inputs[PPC970_INPUT_INT];
|
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break;
|
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|
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default:
|
||||
fprintf(stderr, "XICS interrupt controller does not support this CPU "
|
||||
"bus model\n");
|
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abort();
|
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}
|
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}
|
||||
|
||||
struct icp_state *xics_system_init(int nr_servers, int nr_irqs)
|
||||
{
|
||||
CPUPPCState *env;
|
||||
CPUState *cpu;
|
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int max_server_num;
|
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struct icp_state *icp;
|
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struct ics_state *ics;
|
||||
|
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max_server_num = -1;
|
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for (env = first_cpu; env != NULL; env = env->next_cpu) {
|
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cpu = CPU(ppc_env_get_cpu(env));
|
||||
if (cpu->cpu_index > max_server_num) {
|
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max_server_num = cpu->cpu_index;
|
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}
|
||||
}
|
||||
|
||||
icp = g_malloc0(sizeof(*icp));
|
||||
icp->nr_servers = max_server_num + 1;
|
||||
icp->nr_servers = nr_servers;
|
||||
icp->ss = g_malloc0(icp->nr_servers*sizeof(struct icp_server_state));
|
||||
|
||||
for (env = first_cpu; env != NULL; env = env->next_cpu) {
|
||||
cpu = CPU(ppc_env_get_cpu(env));
|
||||
struct icp_server_state *ss = &icp->ss[cpu->cpu_index];
|
||||
|
||||
switch (PPC_INPUT(env)) {
|
||||
case PPC_FLAGS_INPUT_POWER7:
|
||||
ss->output = env->irq_inputs[POWER7_INPUT_INT];
|
||||
break;
|
||||
|
||||
case PPC_FLAGS_INPUT_970:
|
||||
ss->output = env->irq_inputs[PPC970_INPUT_INT];
|
||||
break;
|
||||
|
||||
default:
|
||||
hw_error("XICS interrupt model does not support this CPU bus "
|
||||
"model\n");
|
||||
exit(1);
|
||||
}
|
||||
}
|
||||
|
||||
ics = g_malloc0(sizeof(*ics));
|
||||
ics->nr_irqs = nr_irqs;
|
||||
ics->offset = XICS_IRQ_BASE;
|
||||
|
||||
@@ -518,6 +518,7 @@ static int spapr_phb_init(SysBusDevice *s)
|
||||
{
|
||||
sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(s);
|
||||
PCIHostState *phb = PCI_HOST_BRIDGE(s);
|
||||
const char *busname;
|
||||
char *namebuf;
|
||||
int i;
|
||||
PCIBus *bus;
|
||||
@@ -575,9 +576,6 @@ static int spapr_phb_init(SysBusDevice *s)
|
||||
}
|
||||
|
||||
sphb->dtbusname = g_strdup_printf("pci@%" PRIx64, sphb->buid);
|
||||
if (!sphb->busname) {
|
||||
sphb->busname = sphb->dtbusname;
|
||||
}
|
||||
|
||||
namebuf = alloca(strlen(sphb->dtbusname) + 32);
|
||||
|
||||
@@ -621,7 +619,26 @@ static int spapr_phb_init(SysBusDevice *s)
|
||||
&sphb->msiwindow);
|
||||
}
|
||||
|
||||
bus = pci_register_bus(DEVICE(s), sphb->busname,
|
||||
/*
|
||||
* Selecting a busname is more complex than you'd think, due to
|
||||
* interacting constraints. If the user has specified an id
|
||||
* explicitly for the phb , then we want to use the qdev default
|
||||
* of naming the bus based on the bridge device (so the user can
|
||||
* then assign devices to it in the way they expect). For the
|
||||
* first / default PCI bus (index=0) we want to use just "pci"
|
||||
* because libvirt expects there to be a bus called, simply,
|
||||
* "pci". Otherwise, we use the same name as in the device tree,
|
||||
* since it's unique by construction, and makes the guest visible
|
||||
* BUID clear.
|
||||
*/
|
||||
if (s->qdev.id) {
|
||||
busname = NULL;
|
||||
} else if (sphb->index == 0) {
|
||||
busname = "pci";
|
||||
} else {
|
||||
busname = sphb->dtbusname;
|
||||
}
|
||||
bus = pci_register_bus(DEVICE(s), busname,
|
||||
pci_spapr_set_irq, pci_spapr_map_irq, sphb,
|
||||
&sphb->memspace, &sphb->iospace,
|
||||
PCI_DEVFN(0, 0), PCI_NUM_PINS);
|
||||
@@ -663,7 +680,6 @@ static void spapr_phb_reset(DeviceState *qdev)
|
||||
}
|
||||
|
||||
static Property spapr_phb_properties[] = {
|
||||
DEFINE_PROP_STRING("busname", sPAPRPHBState, busname),
|
||||
DEFINE_PROP_INT32("index", sPAPRPHBState, index, -1),
|
||||
DEFINE_PROP_HEX64("buid", sPAPRPHBState, buid, -1),
|
||||
DEFINE_PROP_HEX32("liobn", sPAPRPHBState, dma_liobn, -1),
|
||||
@@ -694,14 +710,12 @@ static const TypeInfo spapr_phb_info = {
|
||||
.class_init = spapr_phb_class_init,
|
||||
};
|
||||
|
||||
PCIHostState *spapr_create_phb(sPAPREnvironment *spapr, int index,
|
||||
const char *busname)
|
||||
PCIHostState *spapr_create_phb(sPAPREnvironment *spapr, int index)
|
||||
{
|
||||
DeviceState *dev;
|
||||
|
||||
dev = qdev_create(NULL, TYPE_SPAPR_PCI_HOST_BRIDGE);
|
||||
qdev_prop_set_uint32(dev, "index", index);
|
||||
qdev_prop_set_string(dev, "busname", busname);
|
||||
qdev_init_nofail(dev);
|
||||
|
||||
return PCI_HOST_BRIDGE(dev);
|
||||
|
||||
@@ -39,7 +39,6 @@ typedef struct sPAPRPHBState {
|
||||
|
||||
int32_t index;
|
||||
uint64_t buid;
|
||||
char *busname;
|
||||
char *dtbusname;
|
||||
|
||||
MemoryRegion memspace, iospace;
|
||||
@@ -82,8 +81,7 @@ static inline qemu_irq spapr_phb_lsi_qirq(struct sPAPRPHBState *phb, int pin)
|
||||
return xics_get_qirq(spapr->icp, phb->lsi_table[pin].irq);
|
||||
}
|
||||
|
||||
PCIHostState *spapr_create_phb(sPAPREnvironment *spapr, int index,
|
||||
const char *busname);
|
||||
PCIHostState *spapr_create_phb(sPAPREnvironment *spapr, int index);
|
||||
|
||||
int spapr_populate_pci_dt(sPAPRPHBState *phb,
|
||||
uint32_t xics_phandle,
|
||||
|
||||
@@ -35,6 +35,7 @@ struct icp_state;
|
||||
qemu_irq xics_get_qirq(struct icp_state *icp, int irq);
|
||||
void xics_set_irq_type(struct icp_state *icp, int irq, bool lsi);
|
||||
|
||||
struct icp_state *xics_system_init(int nr_irqs);
|
||||
struct icp_state *xics_system_init(int nr_servers, int nr_irqs);
|
||||
void xics_cpu_setup(struct icp_state *icp, PowerPCCPU *cpu);
|
||||
|
||||
#endif /* __XICS_H__ */
|
||||
|
||||
Reference in New Issue
Block a user